The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Il-San Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Woo-Chan Park, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Kyung-Su Kim, Won-Jong Lee, Tack-Don Han, Sung-Bong Yang
    A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:160-175 [Conf]
  2. Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang
    A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:173-0 [Conf]
  3. Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang
    An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1501-1508 [Journal]
  4. Kil-Whan Lee, Woo-Chan Park, Il-San Kim, Tack-Don Han
    A pixel cache architecture with selective placement scheme based on z-test result. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:1, pp:41-46 [Journal]
  5. Woo-Chan Park, Cheong-Ghil Kim, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Tack-Don Han
    A consistency-free memory architecture for sort-last parallel rendering processors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:272-284 [Journal]

Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002