The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Ulrich Ramacher: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny
    Pulse coupled neural networks with adaptive synapses for image segmentation. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:275-282 [Conf]
  2. Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt
    Wireless platforms: GOPS for cents and MilliWatts. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:351-352 [Conf]
  3. Chr. Werner, R. Göttsche, A. Wörner, Ulrich Ramacher
    Crosstalk noise in future digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:331-335 [Conf]
  4. Arne Heittmann, Ulrich Ramacher, Daniel Matolin, Jörg Schreiter, René Schüffny
    An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. [Citation Graph (0, 0)][DBLP]
    ICANN, 2002, pp:1293-1298 [Conf]
  5. Werner Hemmert, Marcus Holmberg, Ulrich Ramacher
    Temporal Sound Processing by Cochlear Nucleus Octopus Neurons. [Citation Graph (0, 0)][DBLP]
    ICANN (1), 2005, pp:583-588 [Conf]
  6. Ulrich Ramacher
    SEE-1 - A Vision System for Use in Real World Environments. [Citation Graph (0, 0)][DBLP]
    ICANN, 1996, pp:17- [Conf]
  7. Ulrich Ramacher
    Application Specific Embedded Processors for Next Generation Communication Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:- [Conf]
  8. Matthias Wesseling, Ulrich Ramacher, Karl Goser
    Evaluation and Comparison of Selected WSI Reconfiguration Architectures in Terms of Yield and Yield per Area. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1989, pp:74-84 [Conf]
  9. Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer
    SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:774-781 [Conf]
  10. Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder
    Architecture and VLSI Design of a VLSI Neural Signal Processor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1975-1978 [Conf]
  11. Ulrich Ramacher, Wolfgang Raab, Wolfgang Kabatzke
    Prototyp eines Bildrechners für Echtzeitbildverarbeitung in Industrie- und Medientechnik. [Citation Graph (0, 0)][DBLP]
    PEARL, 1999, pp:102-110 [Conf]
  12. Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher
    A low-power memory hierarchy for a fully programmable baseband processor. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:102-106 [Conf]
  13. Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher
    3D Chip Stack Technology Using Through-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:512-518 [Journal]
  14. Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer
    A 100-GOPS Programmable Processor for Vehicle Vision Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:8-16 [Journal]
  15. Ulrich Ramacher, Wolfgang Raab, Joachim K. Anlauf, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Reinhard Männer, Joachim Gläß, Andreas Wurz
    Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1993, v:4, n:4, pp:333-336 [Journal]
  16. Ulrich Ramacher, Peter Schildberg
    Recent Developments In Neurodynamics And Their Impact On The Design Of Neuro-Chips. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1993, v:4, n:4, pp:309-316 [Journal]
  17. Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar
    Design of a general-purpose neural signal processor. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1993, v:5, n:1, pp:17-23 [Journal]
  18. Ulrich Ramacher
    SYNAPSE - A Neurocomputer that Synthesizes Neural Algorithms on a Parallel Systolic Engine. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:14, n:3, pp:306-318 [Journal]
  19. Joachim M. Buhmann, Tilman Lange, Ulrich Ramacher
    Image Segmentation by Networks of Spiking Neurons. [Citation Graph (0, 0)][DBLP]
    Neural Computation, 2005, v:17, n:5, pp:1010-1031 [Journal]
  20. Ulrich Ramacher
    Hamiltonian dynamics of neural networks. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1993, v:6, n:4, pp:547-557 [Journal]
  21. Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer
    100 GOPS vision processor for automotive applications. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:60-68 [Journal]

  22. Challenges and prospects of SDR for mobile phones. [Citation Graph (, )][DBLP]


  23. Software-Defined Radio Prospects for Multistandard Mobile Phones. [Citation Graph (, )][DBLP]


  24. Roundtable: Envisioning the Future for Multiprocessor SoC. [Citation Graph (, )][DBLP]


Search in 0.165secs, Finished in 0.166secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002