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Dake Liu:
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Publications of Author
- Di Wu, Tiejun Hu, Dake Liu
A Single Issue DSP based Multi-standard Media Processor for Mobile Platforms. [Citation Graph (0, 0)][DBLP] ARCS Workshops, 2006, pp:333-342 [Conf]
- Tomas Henriksson, Ulf Nordqvist, Dake Liu
Embedded Protocol Processor for Fast and Efficient Packet Reception. [Citation Graph (0, 0)][DBLP] ICCD, 2002, pp:414-0 [Conf]
- Daniel Wiklund, Dake Liu
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems. [Citation Graph (0, 0)][DBLP] IPDPS, 2003, pp:78- [Conf]
- O. Flordal, Di Wu, Dake Liu
Accelerating CABAC encoding for multi-standard media with configurability. [Citation Graph (0, 0)][DBLP] IPDPS, 2006, pp:- [Conf]
- Di Wu, Johan Eilert, Dake Liu, Dandan Wang, Naofal Al-Dhahir, Hlaing Minn
Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding. [Citation Graph (0, 0)][DBLP] ISVLSI, 2007, pp:325-330 [Conf]
- Daniel Wiklund, Dake Liu
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip. [Citation Graph (0, 0)][DBLP] IWSOC, 2005, pp:252-256 [Conf]
- Daniel Wiklund, Sumant Sathe, Dake Liu
Network on Chip Simulations for Benchmarking. [Citation Graph (0, 0)][DBLP] IWSOC, 2004, pp:269-274 [Conf]
- Mikael Olausson, Anders Edman, Dake Liu
Bit Memory Instructions for a General CPU. [Citation Graph (0, 0)][DBLP] IWSOC, 2004, pp:215-218 [Conf]
- Eric Tell, Anders Nilsson, Dake Liu
A Low Area and Low Power Programmable Baseband Processor Architecture. [Citation Graph (0, 0)][DBLP] IWSOC, 2005, pp:347-351 [Conf]
- Andreas Ehliar, Dake Liu
Flexible route lookup using range search. [Citation Graph (0, 0)][DBLP] Communications and Computer Networks, 2005, pp:345-350 [Conf]
- Johan Eilert, Di Wu, Dake Liu
Efficient Complex Matrix Inversion for MIMO Software Defined Radio. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:2610-2613 [Conf]
- Anders Nilsson, Dake Liu
Area Efficient Fully Programmable Baseband Processors. [Citation Graph (0, 0)][DBLP] SAMOS, 2007, pp:333-342 [Conf]
Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture. [Citation Graph (, )][DBLP]
Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution. [Citation Graph (, )][DBLP]
An fpga based open source network-on-chip architecture. [Citation Graph (, )][DBLP]
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. [Citation Graph (, )][DBLP]
An ASIC perspective on FPGA optimizations. [Citation Graph (, )][DBLP]
Operation Classification for Control Path Synthetization with NoGAP. [Citation Graph (, )][DBLP]
NoGAP: A Micro Architecture Construction Framework. [Citation Graph (, )][DBLP]
Implementation Aspects of Fixed-Complexity Soft-Output MIMO Detection. [Citation Graph (, )][DBLP]
Cost Analysis of Channel Estimation in MIMO-OFDM for Software Defined Radio. [Citation Graph (, )][DBLP]
Implementation of a programmable linear MMSE detector for MIMO-OFDM. [Citation Graph (, )][DBLP]
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