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Nader Bagherzadeh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nader Bagherzadeh, Seng-lai Heng, Chuan-lin Wu
    A Parallel Asynchronous Garbage Collection Algorithm for Distributed Systems. [Citation Graph (1, 12)][DBLP]
    IEEE Trans. Knowl. Data Eng., 1991, v:3, n:1, pp:100-107 [Journal]
  2. Afshin Niktash, Hooman Parizi, Nader Bagherzadeh
    A Reconfigurable Processor for Forward Error Correction. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:1-13 [Conf]
  3. Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka
    A Programmable DSP Architecture for Wireless Communication Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:231-238 [Conf]
  4. Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David Jensen
    Fast and efficient voltage scheduling by evolutionary slack distribution. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:659-662 [Conf]
  5. Dexin Li, Pai H. Chou, Nader Bagherzadeh
    Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:697-704 [Conf]
  6. Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm
    A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:116-125 [Conf]
  7. Nozar Tabrizi, Nader Bagherzadeh, Amir Hosein Kamalizad, Haitao Du
    MaRS: a macro-pipelined reconfigurable system. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:343-349 [Conf]
  8. Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
    Communication speed selection for embedded systems with networked voltage-scalable processors. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:169-174 [Conf]
  9. Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi
    A constraint-based application model and scheduling techniques for power-aware systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:153-158 [Conf]
  10. Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
    A fast parallel reed-solomon decoder on a reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:59-64 [Conf]
  11. F. Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:30-35 [Conf]
  12. Seung Eun Lee, Nader Bagherzadeh
    Increasing the throughput of an adaptive router in network-on-chip (NoC). [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:82-87 [Conf]
  13. Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi
    Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:840-845 [Conf]
  14. Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh
    MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:573-578 [Conf]
  15. Javier Davila, Alfonso de Torres, Jose Manuel Sanchez, Marcos Sanchez-Elez, Nader Bagherzadeh, F. Rivera
    Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys). [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:52-57 [Conf]
  16. Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel L. Anido, Milagros Fernández
    Interactive Ray Tracing on Reconfigurable SIMD MorphoSys. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20144-20149 [Conf]
  17. Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández
    Kernel Scheduling in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:90-96 [Conf]
  18. Chengzhi Pan, Nader Bagherzadeh, Amir Hosein Kamalizad, Arezou Koohi
    Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10468-10475 [Conf]
  19. Marcos Sanchez-Elez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida
    Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10036-10043 [Conf]
  20. Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh
    A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:547-552 [Conf]
  21. Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh
    Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:148-155 [Conf]
  22. F. Rivera, Milagros Fernández, Nader Bagherzadeh
    An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:396-402 [Conf]
  23. Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves
    The MorphoSys Dynamically Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 1999, pp:152-160 [Conf]
  24. Alexander Paar, Haitao Du, Nader Bagherzadeh
    A Component Oriented Simulator for HW/SW Co-Designs. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:79-86 [Conf]
  25. Marcelo Moraes de Azevdeo, Nader Bagherzadeh, Shahram Latifi
    Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:247-252 [Conf]
  26. Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho
    The MorphoSys Parallel Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:727-734 [Conf]
  27. Alexander Paar, Manuel L. Anido, Nader Bagherzadeh
    A Novel Predication Scheme for a SIMD System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:834-843 [Conf]
  28. Hooman Parizi, Afshin Niktash, Nader Bagherzadeh, Fadi J. Kurdahi
    MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:844-848 [Conf]
  29. Steven Wallace, Nader Bagherzadeh
    Instruction Fetching Mechanisms for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:747-756 [Conf]
  30. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
    Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:297-298 [Conf]
  31. Shahram Latifi, Si-Qing Zheng, Nader Bagherzadeh
    Optimal Ring Embedding in Hypercubes with Faulty Links. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:178-184 [Conf]
  32. Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi
    Fault-diameter of the star-connected cycles interconnection network. [Citation Graph (0, 0)][DBLP]
    HICSS (2), 1995, pp:469-478 [Conf]
  33. Manu Gulati, Nader Bagherzadeh
    Performance Study of a Multithreaded Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:291-301 [Conf]
  34. Steven Wallace, Nader Bagherzadeh
    Multiple Branch and Block Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:94-0 [Conf]
  35. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
    Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:575-576 [Conf]
  36. Steven Wallace, Nirav Dagli, Nader Bagherzadeh
    Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:96-101 [Conf]
  37. Manjai Lee, Eric Fiene, Chuan-lin Wu, Geoffrey Brown, Nader Bagherzadeh
    Network Facility for a Reconfigurable Computer Architecture. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1985, pp:264-271 [Conf]
  38. Miguel Sainz, Antonio Susin, Nader Bagherzadeh
    Camera calibration of long image sequences with the presence of occlusions. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 2003, pp:317-320 [Conf]
  39. Arthur Abnous, Roni Potasman, Nader Bagherzadeh, Alexandru Nicolau
    A Percolation Based VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:144-148 [Conf]
  40. Takaaki Kato, Koji Suginuma, Nader Bagherzadeh
    On Design and Performance Analysis of a Superscalar Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:171-178 [Conf]
  41. Alireza Kavianpour, Nader Bagherzadeh
    Parallel Hough Transform for Image Processing on a Pyramid Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:395-398 [Conf]
  42. Shahram Latifi, Marcelo M. de Azevedo, Nader Bagherzadeh
    The Star Connected Cycles: A Fixed-Degree Network for Parallel Processing. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:91-95 [Conf]
  43. Wei-Kang Tsai, Nader Bagherzadeh, Young C. Kim
    Hypermesh: A Combined Quad Tree and Mesh Network for Parallel Processing. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:696-697 [Conf]
  44. Steven Wallace, Nader Bagherzadeh
    Performance Issues of a Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:293-297 [Conf]
  45. Arthur Abnous, Nader Bagherzadeh
    Special Features of a VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:224-227 [Conf]
  46. Nader Bagherzadeh, Kent Hawk
    Parallel Implementation of the Auction Algorithm on the Intel Hypercube. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:443-447 [Conf]
  47. Shahram Latifi, Nader Bagherzadeh
    The Clustered-Star Graph: A New Topology for Large Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:514-518 [Conf]
  48. John Lenell, Nader Bagherzadeh
    A Performance Comparison of Several Superscalar Processor Models with a VLIW Processor. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:44-48 [Conf]
  49. Guangming Lu, Ming-Hau Lee, Hartej Singh, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho
    MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:661-669 [Conf]
  50. F. Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  51. Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
    An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:381-386 [Conf]
  52. Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu
    Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:14-19 [Conf]
  53. Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    A Framework for Scheduling and Context Allocation in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:134-140 [Conf]
  54. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Nader Bagherzadeh, Hartej Singh
    Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:107-114 [Conf]
  55. Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh
    A data scheduler for multi-context reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:177-182 [Conf]
  56. Miguel Sainz, Nader Bagherzadeh, Antonio Susin
    Recovering 3D Metric Structure and Motion from Multiple Uncalibrated Cameras. [Citation Graph (0, 0)][DBLP]
    ITCC, 2002, pp:268-273 [Conf]
  57. Hooman Parizi, Afshin Niktash, Amir Hosein Kamalizad, Nader Bagherzadeh
    A Reconfigurable Architecture for Wireless Communication Systems. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:250-255 [Conf]
  58. Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
    On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:1033-1038 [Conf]
  59. Takaaki Kato, Toshihisa Ono, Nader Bagherzadeh
    Performance analysis and design methodology for a scalable superscalar architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:246-255 [Conf]
  60. Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
    Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:84-98 [Conf]
  61. Shahram Latifi, Nader Bagherzadeh
    Hamiltonicity of the Clustered-Star Graph with Embedding Applications. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1996, pp:734-744 [Conf]
  62. Manuel L. Anido, Nader Bagherzadeh, Nozar Tabrizi, Haitao Du, Marcos Sanchez-Elez
    Interactive Ray Tracing Using a SIMD Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2002, pp:20-28 [Conf]
  63. Amir Hosein Kamalizad, Chengzhi Pan, Nader Bagherzadeh
    Fast Parallel FFT on a Reconfigurable Computation Platform. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:254-259 [Conf]
  64. Dexin Li, Pai H. Chou, Nader Bagherzadeh
    Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:697-704 [Conf]
  65. Marcos Sanchez-Elez, Haitao Du, Nozar Tabrizi, Yun Long, Nader Bagherzadeh, Milagros Fernández
    Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    Computers & Graphics, 2003, v:27, n:5, pp:701-713 [Journal]
  66. Fadi J. Kurdahi, Nader Bagherzadeh, Peter Athanas, Jose L. Muñoz
    Guest Editors' Introduction: Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:17-19 [Journal]
  67. Alireza Kavianpour, Nader Bagherzadeh
    Parallel Algorithms for Line Detection on A Pyramid Architecture. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1994, v:8, n:1, pp:337-349 [Journal]
  68. Marcelo M. de Azevedo, Nader Bagherzadeh, Martin Dowd, Shahram Latifi
    Some Topological Properties of Star Connected Cycles. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1996, v:58, n:2, pp:81-85 [Journal]
  69. Nayla Nassif, Nader Bagherzadeh
    A Grid Embedding into the Star Graph for Image Analysis Solutions. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1996, v:60, n:5, pp:255-260 [Journal]
  70. Shahram Latifi, Nader Bagherzadeh
    On Embedding Rings into a Star-Related Network. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1997, v:99, n:1-2, pp:21-35 [Journal]
  71. S. Shoari, Alireza Kavianpour, Nader Bagherzadeh
    Pyramid simulation of image processing applications. [Citation Graph (0, 0)][DBLP]
    Image Vision Comput., 1994, v:12, n:8, pp:523-529 [Journal]
  72. Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi
    Broadcasting Algorithms for the Star-Connected Cycles Interconnection Network. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:25, n:2, pp:209-222 [Journal]
  73. Alireza Kavianpour, S. Shoari, Nader Bagherzadeh
    A New Approach for Circle Detection on Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:20, n:2, pp:256-260 [Journal]
  74. Alireza Kavianpour, Nader Bagherzadeh
    Finding circular shapes in an image on a pyramid architecture. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 1992, v:13, n:12, pp:843-848 [Journal]
  75. S. Shoari, Nader Bagherzadeh, D. Goodman, Thomas E. Milner, D. J. Smithies, J. S. Nelson
    A parallel algorithm for pulsed laser infrared tomography. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 1998, v:19, n:5-6, pp:521-526 [Journal]
  76. Nader Bagherzadeh, Martin Dowd, Nayla Nassif
    Embedding an Arbitrary Binary Tree into the Star Graph. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:475-481 [Journal]
  77. Nader Bagherzadeh, Nayla Nassif, Shahram Latifi
    A Routing and Broadcasting Scheme on Faulty Star Graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:11, pp:1398-1403 [Journal]
  78. Alireza Kavianpour, Nader Bagherzadeh
    A Systematic Approch for Mapping Application Tasks in Hypercubes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:6, pp:742-746 [Journal]
  79. Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho
    MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:5, pp:465-481 [Journal]
  80. Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes
    Automatic compilation to a coarse-grained reconfigurable system-opn-chip. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:4, pp:560-589 [Journal]
  81. Nader Bagherzadeh, Martin Dowd, Shahram Latifi
    Faster column operations in star networks. [Citation Graph (0, 0)][DBLP]
    Telecommunication Systems, 1998, v:10, n:1, pp:33-44 [Journal]
  82. Arthur Abnous, Nader Bagherzadeh
    Pipelining and Bypassing in a VLIW Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:6, pp:658-664 [Journal]
  83. Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi
    Low Expansion Packings and Embeddings of Hypercubes into Star Graphs: A Performance-Oriented Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:3, pp:261-274 [Journal]
  84. Nader Bagherzadeh, Martin Dowd, Shahram Latifi
    A Well-Behaved Enumeration of Star Graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:5, pp:531-535 [Journal]
  85. Shahram Latifi, Nader Bagherzadeh
    Incomplete Star: An Incrementally Scalable Network Based on the Star Graph. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:1, pp:97-102 [Journal]
  86. Steven Wallace, Nader Bagherzadeh
    Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:6, pp:570-578 [Journal]
  87. F. Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  88. Akira Hatanaka, Nader Bagherzadeh
    A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  89. Afshin Niktash, Hooman Parizi, Nader Bagherzadeh
    Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2586-2589 [Conf]
  90. Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
    Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]
  91. Rafael Maestre, F. Kurdahl, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
    A formal approach to context scheduling for multicontext reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:173-185 [Journal]
  92. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
    A framework for reconfigurable computing: task scheduling and context management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:858-873 [Journal]

  93. A Generic Network Interface Architecture for a Networked Processor Array (NePA). [Citation Graph (, )][DBLP]


  94. Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost. [Citation Graph (, )][DBLP]


  95. Specific Absorption Rate Calculation using Parallel 3D Finite Difference Time Domain Technique. [Citation Graph (, )][DBLP]


  96. Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  97. LocSens - An Indoor Location Tracking System using Wireless Sensors. [Citation Graph (, )][DBLP]


  98. ESTR - Energy Saving Token Ring Protocol for Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  99. Mobile Agents for Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  100. Low power adaptive pipeline based on instruction isolation. [Citation Graph (, )][DBLP]


  101. Parallel FFT Algorithms on Network-on-Chips. [Citation Graph (, )][DBLP]


  102. Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip. [Citation Graph (, )][DBLP]


  103. Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip. [Citation Graph (, )][DBLP]


  104. Scheduling Techniques for Multi-Core Architectures. [Citation Graph (, )][DBLP]


  105. Area and Power-efficient Innovative Network-on-Chip Architecurte. [Citation Graph (, )][DBLP]


  106. Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). [Citation Graph (, )][DBLP]


  107. Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform. [Citation Graph (, )][DBLP]


  108. A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture. [Citation Graph (, )][DBLP]


  109. RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding. [Citation Graph (, )][DBLP]


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