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Praveen Raghavan:
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Publications of Author
- Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors. [Citation Graph (0, 0)][DBLP] ARCS, 2007, pp:57-68 [Conf]
- Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. [Citation Graph (0, 0)][DBLP] ASAP, 2005, pp:179-184 [Conf]
- Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:339-344 [Conf]
- Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. [Citation Graph (0, 0)][DBLP] ESTImedia, 2005, pp:81-86 [Conf]
- David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
Compiler-Driven Leakage Energy Reduction in Banked Register Files. [Citation Graph (0, 0)][DBLP] PATMOS, 2006, pp:107-116 [Conf]
- Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest
Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism. [Citation Graph (0, 0)][DBLP] PATMOS, 2006, pp:12-23 [Conf]
- Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
Very wide register: an asymmetric register file organization for low power embedded processors. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1066-1071 [Conf]
- Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:121-124 [Conf]
- Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest
Semi Custom Design: A Case Study on SIMD Shufflers. [Citation Graph (0, 0)][DBLP] PATMOS, 2007, pp:433-442 [Conf]
- Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals. [Citation Graph (0, 0)][DBLP] SAMOS, 2007, pp:322-332 [Conf]
- Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]
Operation shuffling over cycle boundaries for low energy L0 clustering. [Citation Graph (, )][DBLP]
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. [Citation Graph (, )][DBLP]
Locality optimization in wireless applications. [Citation Graph (, )][DBLP]
SARA: StreAm register allocation. [Citation Graph (, )][DBLP]
Exploiting finite precision information to guide data-flow mapping. [Citation Graph (, )][DBLP]
Compilation Technique for Loop Overhead Minimization. [Citation Graph (, )][DBLP]
Coffee: COmpiler Framework for Energy-Aware Exploration. [Citation Graph (, )][DBLP]
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures. [Citation Graph (, )][DBLP]
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. [Citation Graph (, )][DBLP]
A unified instruction set programmable architecture for multi-standard advanced forward error correction. [Citation Graph (, )][DBLP]
Register file exploration for a multi-standard wireless forward error correction ASIP. [Citation Graph (, )][DBLP]
Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS. [Citation Graph (, )][DBLP]
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