The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Praveen Raghavan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
    A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:57-68 [Conf]
  2. Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina
    Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:179-184 [Conf]
  3. Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
    Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:339-344 [Conf]
  4. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
    Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:81-86 [Conf]
  5. David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
    Compiler-Driven Leakage Energy Reduction in Banked Register Files. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:107-116 [Conf]
  6. Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest
    Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:12-23 [Conf]
  7. Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
    Very wide register: an asymmetric register file organization for low power embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1066-1071 [Conf]
  8. Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
    Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:121-124 [Conf]
  9. Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest
    Semi Custom Design: A Case Study on SIMD Shufflers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:433-442 [Conf]
  10. Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor
    Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:322-332 [Conf]
  11. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
    Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]

  12. Operation shuffling over cycle boundaries for low energy L0 clustering. [Citation Graph (, )][DBLP]


  13. Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. [Citation Graph (, )][DBLP]


  14. Locality optimization in wireless applications. [Citation Graph (, )][DBLP]


  15. SARA: StreAm register allocation. [Citation Graph (, )][DBLP]


  16. Exploiting finite precision information to guide data-flow mapping. [Citation Graph (, )][DBLP]


  17. Compilation Technique for Loop Overhead Minimization. [Citation Graph (, )][DBLP]


  18. Coffee: COmpiler Framework for Energy-Aware Exploration. [Citation Graph (, )][DBLP]


  19. Novel energy-efficient scalable soft-output SSFE MIMO detector architectures. [Citation Graph (, )][DBLP]


  20. Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. [Citation Graph (, )][DBLP]


  21. A unified instruction set programmable architecture for multi-standard advanced forward error correction. [Citation Graph (, )][DBLP]


  22. Register file exploration for a multi-standard wireless forward error correction ASIP. [Citation Graph (, )][DBLP]


  23. Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002