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Murali Jayapala: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
    A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:57-68 [Conf]
  2. Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina
    Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:179-184 [Conf]
  3. Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal
    Instruction buffering exploration for low energy VLIWs with instruction clusters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:824-829 [Conf]
  4. Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck, K. U. Leuven
    Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:338-344 [Conf]
  5. Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
    Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:339-344 [Conf]
  6. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
    Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:81-86 [Conf]
  7. Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins
    CRISP: A Template for Reconfigurable Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:296-305 [Conf]
  8. Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal
    Low Power Coarse-Grained Reconfigurable Instruction Set Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:230-239 [Conf]
  9. Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor
    Instruction Buffering Exploration for Low Energy Embedded Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:409-419 [Conf]
  10. Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck
    L0 Cluster Synthesis and Operation Shuffling. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:311-321 [Conf]
  11. Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal
    A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:258-267 [Conf]
  12. Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll
    Design Style Case Study for Embedded Multi Media Compute Nodes. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:104-113 [Conf]
  13. Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal
    L0 buffer energy optimization through scheduling and exploration. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:905-906 [Conf]
  14. Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck
    Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:338-344 [Conf]
  15. Paul Marchal, Murali Jayapala, Samuel Xavier de Souza, Peng Yang, Francky Catthoor, Geert Deconinck
    Matador: An Exploration Environment for System-Design. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:503-536 [Journal]
  16. Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck
    Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:672-683 [Journal]
  17. Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal
    Very wide register: an asymmetric register file organization for low power embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1066-1071 [Conf]
  18. Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest
    Semi Custom Design: A Case Study on SIMD Shufflers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:433-442 [Conf]
  19. Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai
    Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]

  20. Operation shuffling over cycle boundaries for low energy L0 clustering. [Citation Graph (, )][DBLP]


  21. Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. [Citation Graph (, )][DBLP]


  22. Locality optimization in wireless applications. [Citation Graph (, )][DBLP]


  23. Compilation Technique for Loop Overhead Minimization. [Citation Graph (, )][DBLP]


  24. Coffee: COmpiler Framework for Energy-Aware Exploration. [Citation Graph (, )][DBLP]


  25. Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. [Citation Graph (, )][DBLP]


  26. Instruction Transfer And Storage Exploration for Low Energy VLIWs. [Citation Graph (, )][DBLP]


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