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Marco Platzner: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paul Kaufmann, Marco Platzner
    Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:199-208 [Conf]
  2. Christian Plessl, Marco Platzner
    Zippy - A coarse-grained reconfigurable array with support for hardware virtualization. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:213-218 [Conf]
  3. Herbert Walder, Marco Platzner
    Online Scheduling for Block-Partitioned Reconfigurable Devices . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10290-10295 [Conf]
  4. Rolf Enzler, Christian Plessl, Marco Platzner
    Co-Simulation of a Hybrid Multi-Context Architecture. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:174-180 [Conf]
  5. Christian Plessl, Marco Platzner
    Virtualization of Hardware - Introduction and Survey. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:63-69 [Conf]
  6. Herbert Walder, Samuel Nobs, Marco Platzner
    XF-Board: A Prototyping Platform for Reconfigurable Hardware Operating Systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:306- [Conf]
  7. Herbert Walder, Marco Platzner
    Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:284-287 [Conf]
  8. Gerald Friedl, Marco Platzner, Bernhard Rinner
    A Special-purpose Coprocessor for Qualitative Simulation. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:695-698 [Conf]
  9. Marco Platzner, Bernhard Rinner, Reinhold Weiss
    Parallel Qualitative Simulation. [Citation Graph (0, 0)][DBLP]
    EUROSIM, 1995, pp:231-236 [Conf]
  10. Matthias Dyer, Marco Platzner, Lothar Thiele
    Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:342-344 [Conf]
  11. Christian Plessl, Marco Platzner
    Custom Computing Machines for the Set Covering Problem. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:163-172 [Conf]
  12. Klaus Danne, Marco Platzner
    A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:568-573 [Conf]
  13. Matthias Dyer, Christian Plessl, Marco Platzner
    Partially Reconfigurable Cores for Xilinx Virtex. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:292-301 [Conf]
  14. Michael Eisenring, Marco Platzner
    Optimization of Run-Time Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:565-574 [Conf]
  15. Michael Eisenring, Marco Platzner, Lothar Thiele
    Communication Synthesis for Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:205-214 [Conf]
  16. Rolf Enzler, Christian Plessl, Marco Platzner
    Virtualizing Hardware with Multi-context Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:151-160 [Conf]
  17. Marco Platzner, Giovanni De Micheli
    Acceleration of Satisfiability Algorithms by Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:69-78 [Conf]
  18. Christoph Steiger, Herbert Walder, Marco Platzner
    Heuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:575-584 [Conf]
  19. Herbert Walder, Marco Platzner
    A Runtime Environment for Reconfigurable Hardware Operating Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:831-835 [Conf]
  20. Oskar Mencer, Marco Platzner
    Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  21. Herbert Walder, Christoph Steiger, Marco Platzner
    Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:178- [Conf]
  22. Klaus Danne, Marco Platzner
    Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  23. Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele
    Reconfigurable Hardware in Wearable Computing Nodes. [Citation Graph (0, 0)][DBLP]
    ISWC, 2002, pp:215-222 [Conf]
  24. Klaus Danne, Marco Platzner
    An EDF schedulability test for periodic tasks on reconfigurable hardware devices. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:93-102 [Conf]
  25. Marco Platzner, Bernhard Rinner, Reinhold Weiss
    A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:311-318 [Conf]
  26. Michael Eisenring, Marco Platzner
    An Implementation Framework for Run-time Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  27. Christoph Steiger, Herbert Walder, Marco Platzner, Lothar Thiele
    Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    RTSS, 2003, pp:224-235 [Conf]
  28. Klaus Danne, Marco Platzner
    Periodic Real-Time Scheduling for FPGA Computers. [Citation Graph (0, 0)][DBLP]
    WISES, 2005, pp:117-127 [Conf]
  29. Marco Platzner
    Reconfigurable Accelerators for Combinatorial Problems. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:4, pp:58-60 [Journal]
  30. Marco Platzner, Bernhard Rinner, Reinhold Weiss
    Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim. [Citation Graph (0, 0)][DBLP]
    IEEE Intelligent Systems, 2000, v:15, n:2, pp:62-68 [Journal]
  31. Marco Platzner, Bernhard Rinner, Reinhold Weiss
    Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. [Citation Graph (0, 0)][DBLP]
    J. UCS, 1995, v:1, n:12, pp:811-820 [Journal]
  32. Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, Gerhard Tröster
    The case for reconfigurable hardware in wearable computing. [Citation Graph (0, 0)][DBLP]
    Personal and Ubiquitous Computing, 2003, v:7, n:5, pp:299-308 [Journal]
  33. Marco Platzner, Bernhard Rinner, Reinhold Weiss
    Parallel qualitative simulation. [Citation Graph (0, 0)][DBLP]
    Simul. Pr. Theory, 1997, v:5, n:7-8, pp:623-638 [Journal]
  34. Christoph Steiger, Herbert Walder, Marco Platzner
    Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1393-1407 [Journal]
  35. Michael Eisenring, Marco Platzner
    A Framework for Run-time Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2002, v:21, n:2, pp:145-159 [Journal]
  36. Christian Plessl, Marco Platzner
    Instance-Specific Accelerators for Minimum Covering. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2003, v:26, n:2, pp:109-129 [Journal]
  37. Rolf Enzler, Christian Plessl, Marco Platzner
    System-level performance evaluation of reconfigurable processors. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:63-73 [Journal]
  38. Klaus Danne, Roland Muhlenbernd, Marco Platzner
    Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  39. Oskar Mencer, Marco Platzner, Martin Morf, Michael J. Flynn
    Object-oriented domain specific compilers for programming FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:205-210 [Journal]

  40. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. [Citation Graph (, )][DBLP]


  41. The GOmputer: Accelerating GO with FPGAs. [Citation Graph (, )][DBLP]


  42. A Hardware Accelerator for k-th Nearest Neighbor Thinning. [Citation Graph (, )][DBLP]


  43. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. [Citation Graph (, )][DBLP]


  44. A Many-core Implementation based on the Reconfigurable Mesh Model. [Citation Graph (, )][DBLP]


  45. ReconOS: An RTOS supporting Hard- and Software Threads. [Citation Graph (, )][DBLP]


  46. A portable abstraction layer for hardware threads. [Citation Graph (, )][DBLP]


  47. Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP]


  48. Cooperative multithreading in dynamically reconfigurable systems. [Citation Graph (, )][DBLP]


  49. Program-driven fine-grained power management for the reconfigurable mesh. [Citation Graph (, )][DBLP]


  50. An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure. [Citation Graph (, )][DBLP]


  51. Advanced techniques for the creation and propagation of modules in cartesian genetic programming. [Citation Graph (, )][DBLP]


  52. A Comparison of Evolvable Hardware Architectures for Classification Tasks. [Citation Graph (, )][DBLP]


  53. ARMLang: A language and compiler for programming reconfigurable mesh many-cores. [Citation Graph (, )][DBLP]


  54. Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. [Citation Graph (, )][DBLP]


  55. Realizing reconfigurable mesh algorithms on softcore arrays. [Citation Graph (, )][DBLP]


  56. MOVES: A Modular Framework for Hardware Evolution. [Citation Graph (, )][DBLP]


  57. A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. [Citation Graph (, )][DBLP]


  58. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. [Citation Graph (, )][DBLP]


  59. Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. [Citation Graph (, )][DBLP]


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