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Olivier Sentieys: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
    Modeling of Interconnection Networks in Massively Parallel Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:268-282 [Conf]
  2. Daniel Menard, Daniel Chillet, François Charot, Olivier Sentieys
    Automatic floating-point to fixed-point conversion for DSP code generation. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:270-276 [Conf]
  3. Michel Auguin, Mohamed Belhadj, Judith Benzakki, C. Carrière, Guy Durrieu, Thierry Gautier, Michel Israël, Paul Le Guernic, Michel Lemaître, E. Martin, P. Quinton, Laurence Rideau, François Rousseau, Olivier Sentieys
    Towards a multi-formalism framework for architectural synthesis: the ASAR project. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:25-32 [Conf]
  4. Daniel Menard, Olivier Sentieys
    Automatic Evaluation of the Accuracy of Fixed-Point Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:529-537 [Conf]
  5. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
    A Compilation Framework for a Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1058-1067 [Conf]
  6. Daniel Chillet, Olivier Sentieys, Michel Corazza
    Memory Unit Design for Real Time DSP Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:260-0 [Conf]
  7. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
    A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:51-62 [Conf]
  8. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
    DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  9. Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys
    A low-power and high-speed quaternary interconnection link using efficient converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4689-4692 [Conf]
  10. J. O. Dedou, Daniel Chillet, Olivier Sentieys
    Behavioral synthesis of asynchronous systems: a methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:370-373 [Conf]
  11. E. Kinvi-Boh, M. Aline, Olivier Sentieys, Edgar "Dan" Olson
    MVL circuit design and characterization at the transistor level using SUS-LOC. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:105-110 [Conf]
  12. Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys
    Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:334-339 [Conf]
  13. Sébastien Pillement, Daniel Chillet, Olivier Sentieys
    Behavioral IP Specification and Integration Framework for High-Level Design Reuse. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:388-393 [Conf]
  14. Stéphane Chevobbe, Raphaël David, Frédéric Blanc, Thierry Collette, Olivier Sentieys
    Control Unit for Parallel Embedded System. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:168-176 [Conf]
  15. Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys
    Co-Design of Massively Parallel Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:27-34 [Conf]
  16. Joel Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani
    Compiler and System Techniques for soc Distributed Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:293-302 [Conf]
  17. Daniel Menard, Olivier Sentieys
    DSP Code Generation with Optimized Data Word-Length Selection. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:214-228 [Conf]
  18. Daniel Menard, Taofik Saïdi, Daniel Chillet, Olivier Sentieys
    Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2003, v:22, n:6, pp:783-803 [Journal]
  19. Jean-Marc Philippe, E. Kinvi-Boh, Sébastien Pillement, Olivier Sentieys
    An energy-efficient ternary interconnection link for asynchronous systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  20. R. Rocher, Nicolas Hervé, Daniel Menard, Olivier Sentieys
    Fixed-point configurable hardware components for adaptive filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  21. Nicolas Hervé, Daniel Menard, Olivier Sentieys
    About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:191-200 [Conf]

  22. A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. [Citation Graph (, )][DBLP]


  23. xMAML: A Modeling Language for Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  24. Impact of Transmission Synchronization Error and Cooperative Reception Techniques on the Performance of Cooperative MIMO Systems. [Citation Graph (, )][DBLP]


  25. Minimum Distance Based Precoder for MIMO-OFDM Systems Using a 16-QAM Modulation. [Citation Graph (, )][DBLP]


  26. A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. [Citation Graph (, )][DBLP]


  27. Design of a fault-tolerant coarse-grained. [Citation Graph (, )][DBLP]


  28. Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. [Citation Graph (, )][DBLP]


  29. Efficient dynamic reconfiguration for multi-context embedded FPGA. [Citation Graph (, )][DBLP]


  30. A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems. [Citation Graph (, )][DBLP]


  31. Cooperative MIMO Schemes Optimal Selection for Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  32. Efficient Space Time Combination Technique for Unsynchronized Cooperative Miso Transmission. [Citation Graph (, )][DBLP]


  33. Cooperative MISO and Relay Comparison in Energy Constrained WSNs. [Citation Graph (, )][DBLP]


  34. Reconfigurable Operator Based Multimedia Embedded Processor. [Citation Graph (, )][DBLP]


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