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Dongrui Fan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang, Huimin Cui, Dongrui Fan
    Optimized Register Renaming Scheme for Stack-Based x86 Operations. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:43-56 [Conf]
  2. Dongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao
    An energy efficient TLB design methodology. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:351-356 [Conf]
  3. Xuehai Qian, He Huang, Hao Zhang, Guoping Long, Junchao Zhang, Dongrui Fan
    Design and Implementation of Floating Point Stack on General RISC Architecture. [Citation Graph (0, 0)][DBLP]
    PDP, 2007, pp:238-245 [Conf]
  4. Dongrui Fan, Hongbo Yang, Guangrong Gao, Rongcai Zhao
    Evaluation and Choice of Various Branch Predictors for Low-Power Embedded Processor. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:6, pp:833-838 [Journal]
  5. Xuehai Qian, Hao Zhang, Jingang Yang, He Huang, Junchao Zhang, Dongrui Fan
    Circuit implementation of floating point range reduction for trigonometric functions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3010-3013 [Conf]

  6. A Fast Linear-Space Sequence Alignment Algorithm with Dynamic Parallelization Framework. [Citation Graph (, )][DBLP]


  7. A Low-Complexity Synchronization Based Cache Coherence Solution for Many Cores. [Citation Graph (, )][DBLP]


  8. Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors. [Citation Graph (, )][DBLP]


  9. Design of New Hash Mapping Functions. [Citation Graph (, )][DBLP]


  10. A Performance Model of Dense Matrix Operations on Many-Core Architectures. [Citation Graph (, )][DBLP]


  11. Characterizing and Understanding the Bandwidth Behavior of Workloads on Multi-core Processors. [Citation Graph (, )][DBLP]


  12. High Performance Matrix Multiplication on Many Cores. [Citation Graph (, )][DBLP]


  13. Thread Owned Block Cache: Managing Latency in Many-Core Architecture. [Citation Graph (, )][DBLP]


  14. Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture. [Citation Graph (, )][DBLP]


  15. A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor. [Citation Graph (, )][DBLP]


  16. GFFC: The Global Feedback Based Flow Control in the NoC Design for Many-core Processor. [Citation Graph (, )][DBLP]


  17. Location Consistency Model Revisited: Problem, Solution and Prospects. [Citation Graph (, )][DBLP]


  18. Efficient Parallelization of a Protein Sequence Comparison Algorithm on Manycore Architecture. [Citation Graph (, )][DBLP]


  19. Experience on optimizing irregular computation for memory hierarchy in manycore architecture. [Citation Graph (, )][DBLP]


  20. Architectural support for cilk computations on many-core architectures. [Citation Graph (, )][DBLP]


  21. Study on Fine-Grained Synchronization in Many-Core Architecture. [Citation Graph (, )][DBLP]


  22. Simplified Multi-Ported Cache in High Performance Processor. [Citation Graph (, )][DBLP]


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