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Publications of Author

1. Alexander Thomas, Jürgen Becker
   Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur. [Citation Graph (0, 0)][DBLP]
   ARCS Workshops, 2004, pp:165-174 [Conf]
   
2. Alexander Thomas, Vittorio Ferrari, Bastian Leibe, Tinne Tuytelaars, Bernt Schiele, Luc J. Van Gool
   Towards Multi-View Object Class Detection. [Citation Graph (0, 0)][DBLP]
   CVPR (2), 2006, pp:1589-1596 [Conf]
   
3. Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten
   An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:11120-11121 [Conf]
   
4. Alexander Thomas
   Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime Routing. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:745-746 [Conf]
   
5. Alexander Thomas, Jürgen Becker
   Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:115-124 [Conf]
   
6. Alexander Thomas, Jürgen Becker
   Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2005, pp:118-123 [Conf]
   
7. Jens E. Becker, Carsten Bieser, Alexander Thomas, Klaus D. Müller-Glaser, Jürgen Becker
   Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core. [Citation Graph (0, 0)][DBLP]
   MSE, 2003, pp:134-135 [Conf]
   
8. Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas
   Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2005, pp:35-42 [Conf]
   
9. Alexander Thomas, Thomas Zander, Jürgen Becker
   Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2004, pp:141-146 [Conf]
   
10. Jürgen Becker, Alexander Thomas, Maik Scheer
    Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:237-242 [Conf]
    
11. Jürgen Becker, Alexander Thomas, Maik Scheer
    Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:288-0 [Conf]
    
12. Jürgen Becker, Alexander Thomas
    Scalable Processor Instruction Set Extension. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:2, pp:136-148 [Journal]
    
13. Alexander Thomas, Jürgen Becker
    New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2007, v:49, n:3, pp:165-0 [Journal]
    
14. 
    Coarse-grained reconfiguration. [Citation Graph (, )][DBLP]
    
    
15. 
    Depth-From-Recognition: Inferring Meta-data by Cognitive Feedback. [Citation Graph (, )][DBLP]