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Publications of Author

1. Alberto Nannarelli, Tomás Lang
   Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:60-0 [Conf]
   
2. Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
   Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2005, pp:147-154 [Conf]
   
3. Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
   Fast Radix-4 Retimed Division with Selection by Comparisons. [Citation Graph (0, 0)][DBLP]
   ASAP, 2002, pp:185-196 [Conf]
   
4. Andrea Del Re, Alberto Nannarelli, Marco Re
   A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:686-687 [Conf]
   
5. Alberto Nannarelli, Tomás Lang
   Low-Power Radix-4 Combined Division and Square Root. [Citation Graph (0, 0)][DBLP]
   ICCD, 1999, pp:236-242 [Conf]
   
6. Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
   Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1102-1105 [Conf]
   
7. Alberto Nannarelli, Gian-Carlo Cardarilli, Marco Re
   Power-delay tradeoffs in residue number system. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:413-416 [Conf]
   
8. Alberto Nannarelli, Marco Re, Gian-Carlo Cardarilli
   Tradeoffs between residue number system and traditional FIR filters. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2001, pp:305-308 [Conf]
   
9. Marco Re, Alberto Nannarelli, Gian-Carlo Cardarilli, Roberto Lojacono
   FPGA realization of RNS to binary signed conversion architecture. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:350-353 [Conf]
   
10. Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
    Low-power implementation of polyphase filters in Quadratic Residue Number system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:725-728 [Conf]
    
11. Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
    Power characterization of digital filters implemented on FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:801-804 [Conf]
    
12. Luca Benini, Alberto Macii, Alberto Nannarelli
    Cached-code compression for energy minimization in embedded processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:322-327 [Conf]
    
13. Alberto Nannarelli, Tomás Lang
    Low-power radix-4 divider. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:205-208 [Conf]
    
14. Alberto Nannarelli, Tomás Lang
    Power-delay tradeoffs for radix-4 and radix-8 dividers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:109-111 [Conf]
    
15. Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
    Digit-Recurrence Dividers with Reduced Logical Depth. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:837-851 [Journal]
    
16. Alberto Nannarelli, Tomás Lang
    Low-Power Divider. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:1, pp:2-14 [Journal]
    
17. Tomás Lang, Alberto Nannarelli
    A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:6, pp:727-739 [Journal]
    
18. G. L. Bernocchi, Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
    Low-power adaptive filter based on RNS components. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3211-3214 [Conf]
    
19. 
    Division Unit for Binary Integer Decimals. [Citation Graph (, )][DBLP]
    
    
20. 
    Post-placement temperature reduction techniques. [Citation Graph (, )][DBLP]
    
    
21. 
    ADAPTO: full-adder based reconfigurable architecture for bit level operations. [Citation Graph (, )][DBLP]
    
    
22. 
    A variant of a radix-10 combinational multiplier. [Citation Graph (, )][DBLP]
    
    
23. 
    On-chip Thermal Modeling Based on SPICE Simulation. [Citation Graph (, )][DBLP]