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Milos D. Ercegovac: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pavan Adharapurapu, Milos D. Ercegovac
    A Linear-System Operator Based Scheme for Evaluation of Multinomials. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2005, pp:249-256 [Conf]
  2. Zhijun Huang, Milos D. Ercegovac
    High-Performance Left-to-Right Array Multiplier Design. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2003, pp:4-11 [Conf]
  3. Milos D. Ercegovac, Tomás Lang
    Sign detection and comparison networks with a small number of transitions. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:59-66 [Conf]
  4. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
    High-Radix Iterative Algorithm for Powering Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2003, pp:204-211 [Conf]
  5. Alexandre F. Tenca, Milos D. Ercegovac
    On the Design of High-Radix On-Line Division for Long Precision. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:44-51 [Conf]
  6. Milos D. Ercegovac, Jean-Michel Muller
    Complex Square Root with Operand Prescaling. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:52-62 [Conf]
  7. Milos D. Ercegovac, Jean-Michel Muller
    Variable Radix Real and Complex Digit-Recurrence Division. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:316-321 [Conf]
  8. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
    High-Radix Logarithm with Selection by Rounding. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:101-110 [Conf]
  9. Vijay Raghunathan, Mani B. Srivastava, Milos D. Ercegovac, Anand Raghunathan
    High-Level Synthesis with SIMD Units. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:407-413 [Conf]
  10. M. Feller, Milos D. Ercegovac
    Queue machines: an organization for parallel computation. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1981, pp:37-47 [Conf]
  11. Milos D. Ercegovac, Darko Kirovski, Miodrag Potkonjak
    Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:568-573 [Conf]
  12. F. Meshkinpour, Milos D. Ercegovac
    A functional language for description and design of digital systems: sequential constructs. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:238-244 [Conf]
  13. Raffi Dionysian, Milos D. Ercegovac
    Variable Precision Representation for Efficient VQ Codebook Storage. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 1992, pp:319-328 [Conf]
  14. Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor
    FPGA-Based Structures for On-Line FFT and DCT. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:310-311 [Conf]
  15. Robert McIlhenny, Milos D. Ercegovac
    RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:275-276 [Conf]
  16. Alexandre F. Tenca, Milos D. Ercegovac
    A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:216-225 [Conf]
  17. Aaron Schneider, Robert McIlhenny, Milos D. Ercegovac
    BigSky-An On-Line Arithmetic Design Tool for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:303-304 [Conf]
  18. Dorab Patel, Martine D. F. Schlag, Milos D. Ercegovac
    vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms. [Citation Graph (0, 0)][DBLP]
    FPCA, 1985, pp:238-255 [Conf]
  19. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
    Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:39-47 [Conf]
  20. Alexandre F. Tenca, Milos D. Ercegovac
    Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:159-165 [Conf]
  21. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
    Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:132-137 [Conf]
  22. Jean-Luc Gaudiot, Milos D. Ercegovac
    A scheme for handling arrays in data-flow systems. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1982, pp:724-729 [Conf]
  23. Jean-Luc Gaudiot, Milos D. Ercegovac
    Performance Analysis of a Data-Flow Computer with Variable Resolution Actors. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1984, pp:2-9 [Conf]
  24. David A. Rennels, Milos D. Ercegovac
    From the University of Illinois via JPL and UCLA to Vytautas Magnus University - 50 years of computer engineering by Algirdas Avizienis. [Citation Graph (0, 0)][DBLP]
    IFIP Congress Topical Sessions, 2004, pp:175-190 [Conf]
  25. Jeffrey M. Fischer, Milos D. Ercegovac
    A Component Framework for Communication in Distributed Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:647-654 [Conf]
  26. James J. Liu, Milos D. Ercegovac
    Symbolic Synthesis of Parallel Processing Systems. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:496-500 [Conf]
  27. Leon Alkalaj, Tomás Lang, Milos D. Ercegovac
    Architectural Support for the Management of Tightly-Coupled Fine-Grain Goals in Flat Concurrent Prolog. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:292-301 [Conf]
  28. José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac
    On-line high-radix exponential with selection by rounding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:121-124 [Conf]
  29. Zhijun Huang, Milos D. Ercegovac
    Two-dimensional signal gating for low-power array multiplier design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:489-492 [Conf]
  30. James J. Liu, Milos D. Ercegovac
    ALIAS Environment: A Design Tool for Application Specific Arrays. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:504-511 [Conf]
  31. Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac
    High-Level Synthesis with SIMD Units. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:407-413 [Conf]
  32. Leon Alkalaj, Tomás Lang, Milos D. Ercegovac
    Architectural Support for Goal Management in Flat Concurrent Prolog. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:8, pp:34-47 [Journal]
  33. Milos D. Ercegovac, Tomás Lang
    On-Line Scheme for Computing Rotation Factors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1988, v:5, n:3, pp:209-227 [Journal]
  34. Milos D. Ercegovac, Tomás Lang
    Module to Perform Multiplication, Division, and Square Root in Systolic Arrays for Matrix Computations. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:11, n:3, pp:212-221 [Journal]
  35. Alex Kapelnikov, Richard R. Muntz, Milos D. Ercegovac
    A Modeling Methodology for the Analysis of Concurrent Systems and Computations. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1989, v:6, n:3, pp:568-597 [Journal]
  36. Alex Kapelnikov, Richard R. Muntz, Milos D. Ercegovac
    A Methodology for Performance Analysis of Parallel Compuations with Looping Constructs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1992, v:14, n:2, pp:105-120 [Journal]
  37. Milos D. Ercegovac
    Heterogeneity in supercomputer architectures. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1988, v:7, n:3, pp:367-372 [Journal]
  38. Milos D. Ercegovac, Laurent Imbert, David W. Matula, Jean-Michel Muller, Guoheng Wei
    Improving Goldschmidt Division, Square Root, and Square Root Reciprocal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:759-763 [Journal]
  39. Milos D. Ercegovac
    A General Hardware-Oriented Method for Evaluation of Functions and Computations in a Digital Computer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:7, pp:667-680 [Journal]
  40. Milos D. Ercegovac, Tomás Lang
    On-the-Fly Conversion of Redundant into Conventional Representations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:7, pp:895-897 [Journal]
  41. Milos D. Ercegovac, Tomás Lang
    Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:6, pp:725-740 [Journal]
  42. Milos D. Ercegovac, Tomás Lang
    Radix-4 Square Root Without Initial PLA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:8, pp:1016-1024 [Journal]
  43. Milos D. Ercegovac, Tomás Lang
    Simple Radix-4 Division with Opterands Scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:9, pp:1204-1208 [Journal]
  44. Milos D. Ercegovac, Tomás Lang
    Fast Multiplication Without Carry-Propagate Addition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:11, pp:1385-1390 [Journal]
  45. Milos D. Ercegovac, Tomás Lang
    On-the-Fly Rounding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1497-1503 [Journal]
  46. Milos D. Ercegovac, Tomás Lang, Paolo Montuschi
    Very-High Radix Division with Prescaling and Selection by Rounding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:8, pp:909-918 [Journal]
  47. Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand
    Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:628-637 [Journal]
  48. Zhijun Huang, Milos D. Ercegovac
    High-Performance Low-Power Left-to-Right Array Multiplier Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:3, pp:272-283 [Journal]
  49. Vojin G. Oklobdzija, Milos D. Ercegovac
    A On-Line Square Root Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:1, pp:70-75 [Journal]
  50. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
    Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1085-1096 [Journal]
  51. Cauligi S. Raghavendra, Algirdas Avizienis, Milos D. Ercegovac
    Fault Tolerance in Binary Tree Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:568-572 [Journal]
  52. Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac
    Long and Fast Up/Down Counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:7, pp:722-735 [Journal]
  53. Kishor S. Trivedi, Milos D. Ercegovac
    On-Line Algorithms for Division and Multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:7, pp:681-687 [Journal]
  54. Osaaki Watanuki, Milos D. Ercegovac
    Error Analysis of Certain Floating-Point On-Line Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:4, pp:352-358 [Journal]
  55. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
    Performance-driven mapping for CPLD architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1424-1431 [Journal]
  56. Raffi Dionysian, Milos D. Ercegovac
    Vector quantization with variable-precision classification. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Image Processing, 1996, v:5, n:11, pp:1528-1538 [Journal]
  57. Jeong-Gun Lee, Jeong-A. Lee, Byeong-Seok Lee, Milos D. Ercegovac
    A Design Method for Heterogeneous Adders. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:121-132 [Conf]

  58. Very high radix division with selection by rounding and prescaling. [Citation Graph (, )][DBLP]


  59. On digit-recurrence division implementations for field programmable gate arrays. [Citation Graph (, )][DBLP]


  60. A Hardware-Oriented Method for Evaluating Complex Polynomials. [Citation Graph (, )][DBLP]


  61. An efficient method for evaluating polynomial and rational function approximations. [Citation Graph (, )][DBLP]


  62. Design and Implementation of a Radix-4 Complex Division Unit with Prescaling. [Citation Graph (, )][DBLP]


  63. A radix-8 complex divider for FPGA implementation. [Citation Graph (, )][DBLP]


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