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Ed F. Deprettere: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gerben J. Hekstra, Ed F. Deprettere
    Fast Rotations: Low-cost Arithmetic Methods for Orthonormal Rotation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:116-125 [Conf]
  2. Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis
    High Level Modeling for Parallel Executions of Nested Loop Algorithms. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:79-91 [Conf]
  3. Ed F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen
    Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:186-190 [Conf]
  4. Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere
    Jacobi-Specific Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:323-0 [Conf]
  5. Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere
    Context-Aware Process Networks. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:6-16 [Conf]
  6. Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
    An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:338-349 [Conf]
  7. Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
    Behavioral specification of control interface for signal processing applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:43-49 [Conf]
  8. Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma
    A strategy for determining a Jacobi specific dataflow processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:53-0 [Conf]
  9. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
    A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:17-28 [Conf]
  10. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
    A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:282-292 [Conf]
  11. Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
    Expression Synthesis in Process Networks generated by LAURA. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:15-21 [Conf]
  12. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
    Translating affine nested-loop programs to process networks. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:220-229 [Conf]
  13. Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
    A trace transformation technique for communication refinement. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:134-139 [Conf]
  14. Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
    The construction of a retargetable simulator for an architecture template. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:125-129 [Conf]
  15. Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
    Compaan: deriving process networks from Matlab for embedded signal processing architectures. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:13-17 [Conf]
  16. Todor Stefanov, Ed F. Deprettere
    Deriving process networks from weakly dynamic applications in system-level design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:90-96 [Conf]
  17. Todor Stefanov, Bart Kienhuis, Ed F. Deprettere
    Algorithmic transformation techniques for efficient exploration of alternative application instances. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:7-12 [Conf]
  18. Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
    Multi-processor system design with ESPAM. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:211-216 [Conf]
  19. A. J. van der Hoeven, A. A. de Lange, Ed F. Deprettere, Patrick Dewilde
    A New Model for the High Level Description and Simulation of VLSI Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:738-741 [Conf]
  20. Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
    System Design Using Kahn Process Networks: The Compaan/Laura Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:340-345 [Conf]
  21. Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere
    Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10656-10661 [Conf]
  22. Li-Sheng Shen, F. A. J. Laarakker, Ed F. Deprettere
    Space Partitioning for Mapping Radiosity Computations onto a Pipelined Parallel Architecture (II). [Citation Graph (0, 0)][DBLP]
    Advances in Computer Graphics Hardware (Machines), 1991, pp:175-190 [Conf]
  23. A. C. Yilmaz, S. Hagestein, Ed F. Deprettere, Patrick Dewilde
    A Hardware Algorithm for Fast Realistic Image Synthesis. [Citation Graph (0, 0)][DBLP]
    Advances in Computer Graphics Hardware, 1989, pp:37-60 [Conf]
  24. Kees-Jan van der Kolk, Ed F. Deprettere, Jeong-A. Lee
    A Floating Point Vectoring Algorithm Based on Fast Rotations. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1140-0 [Conf]
  25. Jérôme Lemaitre, Ed F. Deprettere
    FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:1192-1203 [Conf]
  26. Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
    Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:255-263 [Conf]
  27. Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
    Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:690-699 [Conf]
  28. Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
    Communication Synthesis in a multiprocessor environment. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:360-365 [Conf]
  29. Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed F. Deprettere
    Laura: Leiden Architecture Research and Exploration Tool. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:911-920 [Conf]
  30. Paul Lieverse, Todor Stefanov, Pieter van der Wolf, Ed F. Deprettere
    System Level Design with Spade: an M-JPEG Case Study. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:31-38 [Conf]
  31. K. Jainandunsing, Ed F. Deprettere
    Design of a Concurrent Computer for Solving Systems of Linear Equations. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:204-211 [Conf]
  32. Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele
    Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:129-136 [Conf]
  33. Jun Ma, Keshab K. Parhi, Ed F. Deprettere
    Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 1999, pp:347-350 [Conf]
  34. Sylvain Alliot, Ed F. Deprettere
    Architecture Exploration of a Large Scale System. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:217-224 [Conf]
  35. Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
    A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:18-37 [Conf]
  36. Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
    On the (Re-)Use of IP-Components in Re-configurable Platforms. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:264-273 [Conf]
  37. Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin A. de Kock
    Communication Optimization in Compaan Process Networks. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:494-506 [Conf]
  38. Mihai-Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos
    FPL-3E: Towards Language Support for Reconfigurable Packet Processing. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:82-92 [Conf]
  39. Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis
    Translating Imperative Affine Nested Loop Programs into Process Networks. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:89-111 [Conf]
  40. Laurentiu Nicolae, Ed F. Deprettere
    Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:550-560 [Conf]
  41. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
    An Integer Linear Programming Approach to Classify the Communication in Process Networks. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:62-76 [Conf]
  42. Li-Sheng Shen, Ed F. Deprettere, Patrick Dewilde
    A parallel image-rendering algorithm and architecture based on ray tracing and radiosity shading. [Citation Graph (0, 0)][DBLP]
    Computers & Graphics, 1995, v:19, n:2, pp:281-296 [Journal]
  43. Andy D. Pimentel, Louis O. Hertzberger, Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
    Exploring Embedded-Systems Architectures with Artemis. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:11, pp:57-63 [Journal]
  44. Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis
    Deriving Process Networks from Nested Loop Algorithms. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 2000, v:10, n:2/3, pp:165-176 [Journal]
  45. Jichun Bu, Ed F. Deprettere
    A VLSI system architecture for high-speed radiative transfer 3D image synthesis. [Citation Graph (0, 0)][DBLP]
    The Visual Computer, 1989, v:5, n:3, pp:121-133 [Journal]
  46. Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
    Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  47. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
    Classifying interprocess communication in process network representation of nested-loop programs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]
  48. Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
    Requirements for Interfacing IP-Components in Re-configurable Platforms. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:173-184 [Journal]

  49. Floating point Cordic. [Citation Graph (, )][DBLP]


  50. A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. [Citation Graph (, )][DBLP]


  51. Daedalus: toward composable multimedia MP-SoC design. [Citation Graph (, )][DBLP]


  52. Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. [Citation Graph (, )][DBLP]


  53. Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study. [Citation Graph (, )][DBLP]


  54. Introduction to Mastering Cell BE and GPU Execution Platforms. [Citation Graph (, )][DBLP]


  55. Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell. [Citation Graph (, )][DBLP]


  56. Hierarchical run time deadlock detection in process networks. [Citation Graph (, )][DBLP]


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