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Ahmad A. Hiasat: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy
    Design and Implementation of An RNS Division Algorithmm. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:240-249 [Conf]
  2. Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy
    High-Speed Division Algorithm for Residue Number System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1996-1999 [Conf]
  3. Ahmad A. Hiasat
    A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2n - (2p [plusmn] 1)). [Citation Graph (0, 0)][DBLP]
    Comput. J., 2004, v:47, n:1, pp:93-102 [Journal]
  4. Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy
    Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1999, v:42, n:3, pp:232-240 [Journal]
  5. Ahmad A. Hiasat
    An arithmetic residue to binary conversion technique. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:36, n:1-2, pp:13-25 [Journal]
  6. Ahmad A. Hiasat, Omar Hasan
    Bit-serial architecture for rank order and stack filters. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:36, n:1-2, pp:3-12 [Journal]
  7. Ahmad A. Hiasat
    A Suggestion for a New RNS-Based Multiplier for a Family of Moduli. [Citation Graph (0, 0)][DBLP]
    I. J. Comput. Appl., 2004, v:11, n:2, pp:92-97 [Journal]
  8. Ahmad A. Hiasat, Andraos Sweidan
    Residue number system to binary converter for the moduli set (2n-1, 2n-1, 2n+1). [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:1-2, pp:53-58 [Journal]
  9. Andraos Sweidan, Ahmad A. Hiasat
    On the Theory of Error Control Based on Moduli with Common Factors. [Citation Graph (0, 0)][DBLP]
    Reliable Computing, 2001, v:7, n:3, pp:209-218 [Journal]
  10. Ahmad A. Hiasat
    New Efficient Structure for a Modular Multiplier for RNS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:2, pp:170-174 [Journal]
  11. Ahmad A. Hiasat
    High-Speed and Reduced-Area Modular Adder Structures for RNS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:1, pp:84-89 [Journal]
  12. Ahmad A. Hiasat
    VLSI implementation of new arithmetic residue to binary decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:153-158 [Journal]

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