Ahmad A. Hiasat A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2n - (2p [plusmn] 1)). [Citation Graph (0, 0)][DBLP] Comput. J., 2004, v:47, n:1, pp:93-102 [Journal]
Ahmad A. Hiasat A Suggestion for a New RNS-Based Multiplier for a Family of Moduli. [Citation Graph (0, 0)][DBLP] I. J. Comput. Appl., 2004, v:11, n:2, pp:92-97 [Journal]
Ahmad A. Hiasat New Efficient Structure for a Modular Multiplier for RNS. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2000, v:49, n:2, pp:170-174 [Journal]
Ahmad A. Hiasat High-Speed and Reduced-Area Modular Adder Structures for RNS. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2002, v:51, n:1, pp:84-89 [Journal]
Ahmad A. Hiasat VLSI implementation of new arithmetic residue to binary decoders. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:153-158 [Journal]
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