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Takafumi Aoki: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takafumi Aoki, Hiroaki Amada, Tatsuo Higuchi
    Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:200-207 [Conf]
  2. Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh
    High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:187-200 [Conf]
  3. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Multiplier Block Synthesis Using Evolutionary Graph Generation. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:79-82 [Conf]
  4. Shinichi Shionoya, Takafumi Aoki, Tatsuo Higuchi
    Multiwave Interconnection Networks for MCM-based Parallel Processing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:593-607 [Conf]
  5. Hiroshi Nakajima, Koji Kobayashi, Makoto Morikawa, Atsushi Katsumata, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
    Fast and Robust Fingerprint Identification Algorithm and Its Application to Residential Access Controller. [Citation Graph (0, 0)][DBLP]
    ICB, 2006, pp:326-333 [Conf]
  6. Koichi Ito, Ayumi Morita, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi
    A Fingerprint Recognition Algorithm Combining Phase-Based Image Matching and Feature-Based Matching. [Citation Graph (0, 0)][DBLP]
    ICB, 2006, pp:316-325 [Conf]
  7. Kazuyuki Miyazawa, Koichi Ito, Takafumi Aoki, Koji Kobayashi, Hiroshi Nakajima
    A Phase-Based Iris Recognition Algorithm. [Citation Graph (0, 0)][DBLP]
    ICB, 2006, pp:356-365 [Conf]
  8. Kazuyuki Miyazawa, Koichi Ito, Takafumi Aoki, Koji Kobayashi, Hiroshi Nakajima
    An efficient iris recognition algorithm using phase-based image matching. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2005, pp:49-52 [Conf]
  9. Koichi Ito, Ayumi Morita, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Nakajima, Koji Kobayashi
    A fingerprint recognition algorithm using phase-based image matching for low-quality fingerprints. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2005, pp:33-36 [Conf]
  10. Naohode Uchida, Takuma Shibahara, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi
    3D face recognition using passive stereo vision. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2005, pp:950-953 [Conf]
  11. Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi
    A framework of evolutionary graph generation system and its application to circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:201-204 [Conf]
  12. Naofumi Homma, Jun Sakiyama, Taihei Wakamatsu, Takafumi Aoki, Tatsuo Higuchi
    A systematic approach for analyzing fast addition algorithms using counter tree diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:197-200 [Conf]
  13. Koichi Ito, Takafumi Aoki, Tatsuo Higuchi
    Design of a digital reaction-diffusion system for restoring blurred fingerprint images. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:77-80 [Conf]
  14. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Evolutionary graph generation system with transmigration capability for arithmetic circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:171-174 [Conf]
  15. Takafumi Aoki
    Dreams for New-Device-Based Superchips: From Transistors to Enzymes. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:140-149 [Conf]
  16. Takafumi Aoki, Tatsuo Higuchi
    Impact of Interconnection-Free Biomolecular Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:271-276 [Conf]
  17. Takafumi Aoki, Tatsuo Higuchi
    Set-Valued Logic Circuits for Next Generation VLSI Architectures. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:140-147 [Conf]
  18. Takafumi Aoki, Ken-ichi Hoshi, Tatsuo Higuchi
    Redundant Complex Arithmetic and Its Application to Complex Multiplier Design. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:200-207 [Conf]
  19. Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
    Design of Interconnection-Free Biomolecular Computing System. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:173-180 [Conf]
  20. Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi
    High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:345-0 [Conf]
  21. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
    A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:213-220 [Conf]
  22. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
    A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:19- [Conf]
  23. Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
    A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:262-268 [Conf]
  24. Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
    A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:32-38 [Conf]
  25. Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi
    A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:247-252 [Conf]
  26. Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi
    Enzyme Transistor Circuits for Biomolecular Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:47-0 [Conf]
  27. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:2- [Conf]
  28. Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
    A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:269-274 [Conf]
  29. Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:334-339 [Conf]
  30. Shuichi Maeda, Takafumi Aoki, Tatsuo Higuchi
    Set-Valued Logic Networks Based on Optical Wavelength Multiplexing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:282-290 [Conf]
  31. Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
    Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:253-258 [Conf]
  32. Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
    Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:96-0 [Conf]
  33. Y. Ohi, Takafumi Aoki, Tatsuo Higuchi
    Redundant Complex Number Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:14-19 [Conf]
  34. Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi
    Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:91-98 [Conf]
  35. S. Sakurai, Takafumi Aoki, Tatsuo Higuchi
    Wire-Free Computing Circuits Using Optical Wave-Casting. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:8-13 [Conf]
  36. Takashi Takimoto, Takafumi Aoki, Tatsuo Higuchi
    Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:231-238 [Conf]
  37. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:8-15 [Conf]
  38. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of Set-Valued Logic Networks for Wave-Parallel Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:277-282 [Conf]
  39. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:207-214 [Conf]
  40. Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
    An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:430-437 [Conf]
  41. Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi
    Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:54-60 [Conf]
  42. Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi
    Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:210-215 [Conf]
  43. Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
    Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:148-0 [Conf]
  44. Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    PPSN, 2002, pp:831-840 [Conf]
  45. Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. [Citation Graph (0, 0)][DBLP]
    PPSN, 2004, pp:342-351 [Conf]
  46. Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi
    Evolutionary Synthesis of Arithmetic Circuit Structures. [Citation Graph (0, 0)][DBLP]
    Artif. Intell. Rev., 2003, v:20, n:3-4, pp:199-232 [Journal]
  47. Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
    Interconnection-Free Biomolecular Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:11, pp:41-50 [Journal]
  48. Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshiki Terasaki, Tatsuo Higuchi
    Graph-based evolutionary design of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2002, v:6, n:1, pp:86-100 [Journal]
  49. Sei Nagashima, Koichi Ito, Takafumi Aoki, Hideaki Ishii, Koji Kobayashi
    A High-Accuracy Rotation Estimation Algorithm Based on 1D Phase-Only Correlation. [Citation Graph (0, 0)][DBLP]
    ICIAR, 2007, pp:210-221 [Conf]
  50. Kazuyuki Miyazawa, Koichi Ito, Takafumi Aoki, Koji Kobayashi, Atsushi Katsumata
    An Iris Recognition System Using Phase-Based Image Matching. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:325-328 [Conf]
  51. Koichi Ito, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi
    A Palmprint Recognition Algorithm using Phase-Based Image Matching. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:2669-2672 [Conf]
  52. Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
    SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1847-1850 [Conf]
  53. Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh
    DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1807-1810 [Conf]
  54. Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
    A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1859-1862 [Conf]
  55. Akashi Satoh, Takeshi Sugawara, Takafumi Aoki
    High-Speed Pipelined Hardware Architecture for Galois Counter Mode. [Citation Graph (0, 0)][DBLP]
    ISC, 2007, pp:118-129 [Conf]

  56. Culinary art designer. [Citation Graph (, )][DBLP]


  57. Wearable haptic device to present contact sensation based on cutaneous sensation using thin wire. [Citation Graph (, )][DBLP]


  58. High-Performance Concurrent Error Detection Scheme for AES Hardware. [Citation Graph (, )][DBLP]


  59. Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. [Citation Graph (, )][DBLP]


  60. Chosen-message SPA attacks against FPGA-based RSA hardware implementations. [Citation Graph (, )][DBLP]


  61. Application of symbolic computer algebra to arithmetic circuit verification. [Citation Graph (, )][DBLP]


  62. Systematic design of high-radix Montgomery multipliers for RSA processors. [Citation Graph (, )][DBLP]


  63. A Sub-Pixel Stereo Correspondence Technique Based on 1D Phase-only Correlation. [Citation Graph (, )][DBLP]


  64. A Phase-Based Image Registration Algorithm for Dental Radiograph Identification. [Citation Graph (, )][DBLP]


  65. A robot-based 3D body scanning system using passive stereo vision. [Citation Graph (, )][DBLP]


  66. A palmprint recognition algorithm using phase-based correspondence matching. [Citation Graph (, )][DBLP]


  67. A palmprint recognition algorithm using Principal Component Analysis of phase information. [Citation Graph (, )][DBLP]


  68. Performance evaluation using Mandelbrot images for image registration algorithms. [Citation Graph (, )][DBLP]


  69. A practical method to reducing metal artifact for dental CT scanners. [Citation Graph (, )][DBLP]


  70. Medical image registration using Phase-Only Correlation for distorted dental radiographs. [Citation Graph (, )][DBLP]


  71. A practical palmprint recognition algorithm using phase information. [Citation Graph (, )][DBLP]


  72. Enhanced power analysis attack using chosen message against RSA hardware implementations. [Citation Graph (, )][DBLP]


  73. Arithmetic module generator with algorithm optimization capability. [Citation Graph (, )][DBLP]


  74. High-performance ASIC implementations of the 128-bit block cipher CLEFIA. [Citation Graph (, )][DBLP]


  75. High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. [Citation Graph (, )][DBLP]


  76. Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. [Citation Graph (, )][DBLP]


  77. Multiple-Valued Constant-Power Adder for Cryptographic Processors. [Citation Graph (, )][DBLP]


  78. Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors. [Citation Graph (, )][DBLP]


  79. Culinary art designer. [Citation Graph (, )][DBLP]


  80. Heaven's mirror: mirror illusion realized outside of the mirror. [Citation Graph (, )][DBLP]


  81. Haptic ring: touching virtual creatures in mixed reality environments. [Citation Graph (, )][DBLP]


  82. A stereo one-shot multi-band camera system for accurate color reproduction. [Citation Graph (, )][DBLP]


  83. Virtual Reality in Physical Mirrors. [Citation Graph (, )][DBLP]


  84. Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. [Citation Graph (, )][DBLP]


  85. Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. [Citation Graph (, )][DBLP]


  86. VLSI circuit design using an object-oriented framework of evolutionary graph generation system. [Citation Graph (, )][DBLP]


  87. An LVQ-based technique for human motion segmentation. [Citation Graph (, )][DBLP]


  88. Pixel-wise human motion segmentation using learning vector quantization. [Citation Graph (, )][DBLP]


  89. Phase-based alignment of two signals having partially overlapped spectra. [Citation Graph (, )][DBLP]


  90. Enhanced Correlation Power Analysis Using Key Screening Technique. [Citation Graph (, )][DBLP]


  91. Physics-driven Multi Dimensional Keyframe Animation for Artist-directable Interactive Character. [Citation Graph (, )][DBLP]


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