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Michael J. Schulte: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mark G. Arnold, Jesus Garcia, Michael J. Schulte
    The Interval Logarithmic Number System. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2003, pp:253-261 [Conf]
  2. Mark A. Erle, Eric M. Schwarz, Michael J. Schulte
    Decimal Multiplication with Efficient Partial Product Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2005, pp:21-28 [Conf]
  3. K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte
    Analysis of Column Compression Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:33-39 [Conf]
  4. Thomas Lynch, Ashraf Ahmed, Michael J. Schulte, Thomas K. Callaway, Robert Tisdale
    The K5 transcendental functions. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:163-0 [Conf]
  5. Michael J. Schulte, Earl E. Swartzlander Jr.
    Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:222-229 [Conf]
  6. Michael J. Schulte, James E. Stine
    Symmetric Bipartite Tables for Accurate Function Approximation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:175-183 [Conf]
  7. Michael J. Schulte, Kent E. Wires
    High-Speed Inverse Square Roots. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:124-0 [Conf]
  8. E. George Walters III, Michael J. Schulte
    Efficient Function Approximation Using Truncated Multipliers and Squarers. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2005, pp:232-239 [Conf]
  9. Mark A. Erle, Michael J. Schulte
    Decimal Multiplication Via Carry-Save Addition. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:348-0 [Conf]
  10. Javier Hormigo, Julio Villalba, Michael J. Schulte
    A Hardware Algorithm for Variable-Precision Logarithm. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:215-224 [Conf]
  11. Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael J. Schulte, John Glossner
    Instruction Set Extensions for Reed-Solomon Encoding and Decoding. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:364-369 [Conf]
  12. Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis
    A Low-Power Carry Skip Adder with Fast Saturation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:269-279 [Conf]
  13. Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner
    Combined Multiplication and Sum-of-Squares Units. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:204-214 [Conf]
  14. Michael J. Schulte, Earl E. Swartzlander Jr.
    A Processor for Staggered Interval Arithmetic. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:104-112 [Conf]
  15. Michael J. Schulte, James E. Stine
    Accurate Function Approximations by Symmetric Table Lookup and Addition. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:144-153 [Conf]
  16. Liang-Kai Wang, Michael J. Schulte
    Decimal Floating-Point Division Using Newton-Raphson Iteration. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:84-95 [Conf]
  17. Liang-Kai Wang, Michael J. Schulte
    Decimal Floating-Point Square Root Using Newton-Raphson Iteration. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:309-315 [Conf]
  18. Suman Mamidi, Emily R. Blem, Michael J. Schulte, C. John Glossner, Daniel Iancu, Andrei Iancu, Mayan Moudgill, Sanjay Jinturkar
    Instruction set extensions for software defined radio on a multithreaded processor. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:266-273 [Conf]
  19. Michael J. Schulte, Pablo I. Balzola, Jie Ruan, C. John Glossner
    Parallel saturating multioperand adders. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:172-179 [Conf]
  20. C. John Glossner, Mayan Moudgill, Daniel Iancu, Gary Nacer, Sanjay Jinturkar, Stuart Stanley, Michael Samori, Tanuj Raja, Michael J. Schulte, Stamatis Vassiliadis
    Future wireless convergence platforms. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:7-12 [Conf]
  21. Ahmet Akkas, Michael J. Schulte
    A Quadruple Precision and Dual Double Precision Floating-Point Multiplier. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:76-81 [Conf]
  22. Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis
    A Static Low-Power, High-Performance 32-bit Carry Skip Adder. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:615-619 [Conf]
  23. Kent E. Wires, Michael J. Schulte, Don McCarley
    FPGA Resource Reduction Through Truncated Multiplication. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:574-583 [Conf]
  24. James E. Stine, Michael J. Schulte
    A Combined Interval and Floating Point Multiplier. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:208-0 [Conf]
  25. Navindra Yadav, Michael J. Schulte, John Glossner
    Parallel Saturating Fractional Arithmetic Units. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:214-217 [Conf]
  26. Dean Batten, Sanjay Jinturkar, C. John Glossner, Michael J. Schulte, Paul D'Arcy
    A New Approach to DSP Intrinsic Functions. [Citation Graph (0, 0)][DBLP]
    HICSS, 2000, pp:- [Conf]
  27. Pablo I. Balzola, Michael J. Schulte, Jie Ruan, C. John Glossner, Erdem Hokenek
    Design Alternatives for Parallel Saturating Multioperand Adders. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:172-177 [Conf]
  28. Robert D. Kenney, Michael J. Schulte, Mark A. Erle
    A High-Frequency Decimal Multiplier. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:26-29 [Conf]
  29. Michael J. Schulte, Earl E. Swartzlander Jr.
    A coprocessor for accurate and reliable numerical computations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:686-0 [Conf]
  30. Kent E. Wires, Michael J. Schulte, James E. Stine
    Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:497-500 [Conf]
  31. James E. Stine, Michael J. Schulte
    A combined two's complement and floating-point comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:89-92 [Conf]
  32. Robert D. Kenney, Michael J. Schulte
    Multioperand Decimal Addition. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:251-253 [Conf]
  33. Shankar Krithivasan, Michael J. Schulte, John Glossner
    A Subword-Parallel Multiplication and Sum-of-Squares Unit. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:273-274 [Conf]
  34. John Thompson, Nandini Karra, Michael J. Schulte
    A 64-bit Decimal Floating-Point Adder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:297-298 [Conf]
  35. Michael J. Schulte, C. John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis
    A Low-Power Multithreaded Processor for Baseband Communication Systems. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:393-402 [Conf]
  36. C. John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael J. Schulte, Stamatis Vassiliadis
    Sandbridge Software Tools. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:269-278 [Conf]
  37. C. John Glossner, Michael J. Schulte, Stamatis Vassiliadis
    A Java-Enabled DSP. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:307-326 [Conf]
  38. Ahmet Akkas, Michael J. Schulte
    Dual-mode floating-point multiplier architectures with parallel operations. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:10, pp:549-562 [Journal]
  39. Thomas Lynch, Michael J. Schulte
    A High Radix On-Line Arithmetic for Credible and Accurate Computing. [Citation Graph (0, 0)][DBLP]
    J. UCS, 1995, v:1, n:7, pp:439-453 [Journal]
  40. Michael J. Schulte, Vitaly Zelov, Ahmet Akkas, James Craig Burley
    The Interval-Enhanced GNU Fortran Compiler. [Citation Graph (0, 0)][DBLP]
    Reliable Computing, 1999, v:5, n:3, pp:311-322 [Journal]
  41. Michael J. Schulte
    Hardware interval multipliers. [Citation Graph (0, 0)][DBLP]
    RITA, 1996, v:3, n:2, pp:73-90 [Journal]
  42. Mustafa Gök, Michael J. Schulte, Mark G. Arnold
    Integer Multipliers with Overflow Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:8, pp:1062-1066 [Journal]
  43. Robert D. Kenney, Michael J. Schulte
    High-Speed Multioperand Decimal Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:8, pp:953-963 [Journal]
  44. Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato
    Integer Multiplication with Overflow Detection or Saturation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:681-691 [Journal]
  45. Michael J. Schulte, Earl E. Swartzlander Jr.
    A Family of Variable-Precision Interval Arithmetic Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:5, pp:387-397 [Journal]
  46. Michael J. Schulte, Earl E. Swartzlander Jr.
    Hardware Designs for Exactly Rounded Elemantary Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:8, pp:964-973 [Journal]
  47. Michael J. Schulte, James E. Stine
    Approximating Elementary Functions with Symmetric Bipartite Tables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:8, pp:842-847 [Journal]
  48. Liang-Kai Wang, Michael J. Schulte
    Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:56-68 [Conf]
  49. Mark A. Erle, Michael J. Schulte, Brian J. Hickmann
    Decimal Floating-Point Multiplication Via Carry-Save Addition. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:46-55 [Conf]
  50. John Glossner, Daniel Iancu, Mayan Moudgill, Michael Schulte, Stamatis Vassiliadis
    Trends in Low Power Handset Software Defined Radio. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:313-321 [Conf]
  51. Kent E. Wires, Michael J. Schulte
    Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:3, pp:257-272 [Journal]

  52. Exact rounding of certain elementary functions. [Citation Graph (, )][DBLP]


  53. A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator. [Citation Graph (, )][DBLP]


  54. Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit. [Citation Graph (, )][DBLP]


  55. Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems. [Citation Graph (, )][DBLP]


  56. A Combined Decimal and Binary Floating-Point Multiplier. [Citation Graph (, )][DBLP]


  57. FPGA Design Analysis of the Clustering Algorithm for the CERN Large Hadron Collider. [Citation Graph (, )][DBLP]


  58. Benchmarks and performance analysis of decimal floating-point applications. [Citation Graph (, )][DBLP]


  59. Hardware design of a Binary Integer Decimal-based floating-point adder. [Citation Graph (, )][DBLP]


  60. A parallel IEEE P754 decimal floating-point multiplier. [Citation Graph (, )][DBLP]


  61. Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier. [Citation Graph (, )][DBLP]


  62. Improved combined binary/decimal fixed-point multipliers. [Citation Graph (, )][DBLP]


  63. Software Solutions for Converting a MIMO-OFDM Channel into Multiple SISO-OFDM Channels. [Citation Graph (, )][DBLP]


  64. Implementing communications systems on an SDR SoC. [Citation Graph (, )][DBLP]


  65. The Emerging Landscape of Computer Performance Evaluation. [Citation Graph (, )][DBLP]


  66. A New Era of Performance Evaluation. [Citation Graph (, )][DBLP]


  67. Optimal initial approximations for the Newton-Raphson division algorithm. [Citation Graph (, )][DBLP]


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