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Neil Burgess: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrew Beaumont-Smith, Neil Burgess
    A GaAs 32-bit Adder. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:10-17 [Conf]
  2. Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim
    Reduced Latency IEEE Floating-Point Standard Adder Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:35-0 [Conf]
  3. Neil Burgess
    Scaling an RNS Number Using the Core Function. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2003, pp:262-0 [Conf]
  4. Neil Burgess
    Scaled and Unscaled Residue Number System to Binary Conversion Techniques using the Core Function. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:250-0 [Conf]
  5. S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian
    A GaAs IEEE Floating Point Standard Single Precision Multiplier. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:91-97 [Conf]
  6. Lai-Sze Au, Neil Burgess
    Unified Radix-4 Multiplier for GF(p) and GF(2^n). [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:226-236 [Conf]
  7. Neil Burgess
    PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:197-207 [Conf]
  8. B. R. Lee, Neil Burgess
    Improved Small Multiplier Based Multiplication, Squaring and Division. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:91-0 [Conf]
  9. Barry Lee, Neil Burgess
    A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:808-817 [Conf]
  10. Wen-Kuo Lin, Neil Burgess
    3D Listless Zerotree Coding for Low Bit Rate Video. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1999, pp:762-766 [Conf]
  11. Wen-Kuo Lin, Alireza Moini, Neil Burgess
    Tree-Pruning Listless Zerotree Coding. [Citation Graph (0, 0)][DBLP]
    ICME, 2001, pp:- [Conf]
  12. Wen-Kuo Lin, Brian Wai-Him Ng, Neil Burgess
    Reduced Memory Zerotree Coding Algorithm for Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    ICMCS, Vol. 2, 1999, pp:57-61 [Conf]
  13. Suzanna Becker, Neil Burgess
    Modelling Spatial Recall, Mental Imagery and Neglect. [Citation Graph (0, 0)][DBLP]
    NIPS, 2000, pp:96-102 [Conf]
  14. Neil Burgess
    A solvable connectionist model of immediate recall of ordered lists. [Citation Graph (0, 0)][DBLP]
    NIPS, 1994, pp:51-58 [Conf]
  15. Neil Burgess, Tom Hartley
    Orientational and Geometric Determinants of Place and Head-direction. [Citation Graph (0, 0)][DBLP]
    NIPS, 2001, pp:165-172 [Conf]
  16. Neil Burgess, John O'Keefe, Michael Recce
    Using Hippocampal `Plane Cells' for Navigation, Exploiting Phase Coding. [Citation Graph (0, 0)][DBLP]
    NIPS, 1992, pp:929-936 [Conf]
  17. Nariman Habili, Alireza Moini, Neil Burgess
    Automatic thresholding for change detection in digital video. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:133-142 [Conf]
  18. Wen-Kuo Lin, Alireza Moini, Neil Burgess
    Wavelet-transform-based video content extraction for 3D wavelet video coding. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:959-966 [Conf]
  19. Colin Lever, Neil Burgess, Francesca Cacucci, Tom Hartley, John O'Keefe
    What can the hippocampal representation of environmental geometry tell us about Hebbian learning? [Citation Graph (0, 0)][DBLP]
    Biological Cybernetics, 2002, v:87, n:5-6, pp:356-372 [Journal]
  20. Neil Burgess, James G. Donnett, John O'Keefe
    Using a Mobile Robot to Test a Model of the Rat Hippocampus. [Citation Graph (0, 0)][DBLP]
    Connect. Sci., 1998, v:10, n:3-4, pp:291-300 [Journal]
  21. Neil Burgess
    A Constructive Algorithm that Converges for Real-Valued Input Patterns. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1994, v:5, n:1, pp:59-66 [Journal]
  22. Neil Burgess, Mario Notturno Granieri, Stefano Patarnello
    3-D Object Classification: Application of a Constructive Algorithm. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1991, v:2, n:4, pp:275-282 [Journal]
  23. Neil Burgess, Silvano Di Zenzo, Paolo Ferragina, Mario Notturno Granieri
    The Generalization of a Constructive Algorithm in Pattern Classification Problems. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 1992, v:3, n:Supplement, pp:65-70 [Journal]
  24. Neil Burgess, Michael Recce, John O'Keefe
    A model of hippocampal function. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1994, v:7, n:6-7, pp:1065-1081 [Journal]
  25. Silvano Di Zenzo, Neil Burgess, Paolo Ferragina, Mario Notturno Granieri
    Recognition by constructive neural algorithms. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 1993, v:14, n:12, pp:997-1007 [Journal]
  26. Neil Burgess, Ted Williams
    Choices of Operand Truncation in the SRT Division Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:7, pp:933-938 [Journal]
  27. Michael J. Liebelt, Neil Burgess
    Detecting Exitory Stuck-At Faults in Semimodular Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:4, pp:442-448 [Journal]
  28. Braden Phillips, Neil Burgess
    Minimal Weight Digit Set Conversions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:666-677 [Journal]
  29. Neil Burgess
    Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:266-277 [Journal]
  30. Neil Burgess, Chris N. Hinds
    Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:87-96 [Conf]

  31. A 32-bit GaAs IEEE floating point multiplier using Trailing-1's rounding algorithm. [Citation Graph (, )][DBLP]


  32. Predictions derived from modelling the hippocampal role in navigation. [Citation Graph (, )][DBLP]


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