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T. Srikanthan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. M. Bhardwaj, T. Srikanthan, C. T. Clarke
    A Reverse Converter for the 4-moduli Superset {2^n-1, 2^n, 2^n+1, 2^(n+1)+1}. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:168-175 [Conf]
  2. M. Bhardwaj, T. Srikanthan, C. T. Clarke
    VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:176-0 [Conf]
  3. Babu Mailachalam, T. Srikanthan
    A Robust Parallel Architecture for Adaptive Color Quantization. [Citation Graph (0, 0)][DBLP]
    ITCC, 2000, pp:164-173 [Conf]
  4. Jimson Mathew, D. Radhakrishnan, T. Srikanthan
    Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}. [Citation Graph (0, 0)][DBLP]
    NSIP, 1999, pp:185-188 [Conf]
  5. N. Sudha, T. Srikanthan, Babu Mailachalam
    A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:48, n:11-12, pp:337-352 [Journal]
  6. S. K. Lam, T. Srikanthan
    A linear approximation based hybrid approach for binary logarithmic conversion. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:26, n:8, pp:353-361 [Journal]
  7. Babu Mailachalam, T. Srikanthan
    Area-time issues in the VLSI implementation of self organizing map neural networks. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:26, n:9-10, pp:399-406 [Journal]

  8. Elimination of sign precomputation in flat CORDIC. [Citation Graph (, )][DBLP]


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