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## Search the dblp DataBase
Peter-Michael Seidel:
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## Publications of Author- Guy Even, Peter-Michael Seidel
**A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 1999, pp:225-232 [Conf] - Guy Even, Peter-Michael Seidel, Warren E. Ferguson
**A Parametric Error Analysis of Goldschmidt?s Division Algorithm.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 2003, pp:165-0 [Conf] - Peter-Michael Seidel
**High-Radix Implementation of IEEE Floating-Point Addition.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 2005, pp:99-106 [Conf] - Peter-Michael Seidel, Guy Even
**On the Design of Fast IEEE Floating-Point Adders.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 2001, pp:184-194 [Conf] - Peter-Michael Seidel, Lee D. McFearin, David W. Matula
**Binary Multiplication Radix-32 and Radix-256.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 2001, pp:23-32 [Conf] - Peter-Michael Seidel
**How to Half the Latency of IEEE Compliant Floating-Point Multiplication.**[Citation Graph (0, 0)][DBLP] EUROMICRO, 1998, pp:10329-10332 [Conf] - Steven D. Krueger, Peter-Michael Seidel
**Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs.**[Citation Graph (0, 0)][DBLP] FCCM, 2004, pp:239-246 [Conf] - Nathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel
**Challenges in the Formal Verification of Complete State-of-the-Art Processors.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:603-608 [Conf] - Guy Even, Peter-Michael Seidel
**Pipelined Multiplicative Division with IEEE Rounding.**[Citation Graph (0, 0)][DBLP] ICCD, 2003, pp:240-0 [Conf] - Nikhil Kikkeri, Peter-Michael Seidel
**Formal Hardware Verification based on Signal Correlation Properties.**[Citation Graph (0, 0)][DBLP] ICCD, 2004, pp:402-408 [Conf] - Nikhil Kikkeri, Peter-Michael Seidel
**Formal Verification of Parametric Multiplicative Division Implementations.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:599-602 [Conf] - Peter-Michael Seidel, Kenneth Fazel
**Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters.**[Citation Graph (0, 0)][DBLP] ISVLSI, 2004, pp:277-278 [Conf] - Mark A. Hillebrand, Thomas Schurger, Peter-Michael Seidel
**How to Half Wire Lengths in the Layout of Cyclic Shifter.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2001, pp:339-344 [Conf] - Guy Even, Silvia M. Müller, Peter-Michael Seidel
**A dual precision IEEE floating-point multiplier.**[Citation Graph (0, 0)][DBLP] Integration, 2000, v:29, n:2, pp:167-180 [Journal] - Wolfgang J. Paul, Peter-Michael Seidel
**To Booth or not to Booth.**[Citation Graph (0, 0)][DBLP] Integration, 2002, v:32, n:1-2, pp:5-40 [Journal] - Peter-Michael Seidel
**High-speed redundant reciprocal approximation.**[Citation Graph (0, 0)][DBLP] Integration, 1999, v:28, n:1, pp:1-12 [Journal] - Guy Even, Peter-Michael Seidel, Warren E. Ferguson
**A parametric error analysis of Goldschmidt's division algorithm.**[Citation Graph (0, 0)][DBLP] J. Comput. Syst. Sci., 2005, v:70, n:1, pp:118-139 [Journal] - Guy Even, Peter-Michael Seidel
**A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2000, v:49, n:7, pp:638-650 [Journal] - Peter-Michael Seidel, Guy Even
**Delay-Optimized Implementation of IEEE Floating-Point Addition.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2004, v:53, n:2, pp:97-113 [Journal] - Peter-Michael Seidel, Lee D. McFearin, David W. Matula
**Secondary Radix Recodings for Higher Radix Multipliers.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2005, v:54, n:2, pp:111-123 [Journal] **An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder.**[Citation Graph (, )][DBLP]**An FPGA implementation of pipelined multiplicative division with IEEE Rounding.**[Citation Graph (, )][DBLP]
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