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Earl E. Swartzlander Jr.: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte
    Analysis of Column Compression Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:33-39 [Conf]
  2. Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr.
    Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:115-0 [Conf]
  3. Thomas K. Callaway, Earl E. Swartzlander Jr.
    Power-Delay Characteristics of CMOS Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1997, pp:26-0 [Conf]
  4. Youngmoon Choi, Earl E. Swartzlander Jr.
    Parallel Prefix Adder Design with Matrix Representation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2005, pp:90-98 [Conf]
  5. Michael J. Schulte, Earl E. Swartzlander Jr.
    Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:222-229 [Conf]
  6. Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall
    Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:335-343 [Conf]
  7. Ayman M. El-Khashab, Earl E. Swartzlander Jr.
    An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:378-388 [Conf]
  8. Yuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri
    Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:54-65 [Conf]
  9. Chang Yong Kang, Earl E. Swartzlander Jr.
    An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:111-119 [Conf]
  10. Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.
    Realization of a nonlinear digital filter on a DSP array processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:24-33 [Conf]
  11. Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka
    A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:235-0 [Conf]
  12. Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.
    Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:35-0 [Conf]
  13. Tung N. Pham, Earl E. Swartzlander Jr.
    Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:105-108 [Conf]
  14. Moboluwaji O. Sanu, Earl E. Swartzlander Jr.
    Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:134-139 [Conf]
  15. Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase
    Parallel Montgomery Multipliers. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:63-72 [Conf]
  16. Michael J. Schulte, Earl E. Swartzlander Jr.
    A Processor for Staggered Interval Arithmetic. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:104-112 [Conf]
  17. Earl E. Swartzlander Jr.
    Systolic FFT Processors: Past, Present and Future. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:153-158 [Conf]
  18. Earl E. Swartzlander Jr., John A. Eldon, De D. Hsu
    VLSI Testing: A Decade of Experience. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1985, pp:392-396 [Conf]
  19. W. Lynn Gallagher, Earl E. Swartzlander Jr.
    Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:243-251 [Conf]
  20. W. Lynn Gallagher, Earl E. Swartzlander Jr.
    Error-Correcting Goldschmidt Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:224-232 [Conf]
  21. W. Lynn Gallagher, Earl E. Swartzlander Jr.
    Power Consumption in Fast Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:256-264 [Conf]
  22. Yuang-Ming Hsu, Earl E. Swartzlander Jr.
    VLSI Concurrent Error Correcting Adders and Multipliers. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:287-294 [Conf]
  23. Yuang-Ming Hsu, Earl E. Swartzlander Jr.
    Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:159-167 [Conf]
  24. Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri
    Fault-Tolerant High-Performance Cordic Processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:164-172 [Conf]
  25. Tat Ngai, Earl E. Swartzlander Jr., Chen He
    Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:78-83 [Conf]
  26. Vincenzo Piuri, Earl E. Swartzlander Jr.
    Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:265-273 [Conf]
  27. Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.
    Quadruple Time Redundancy Adders. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:250-256 [Conf]
  28. Gwangwoo Choe, Earl E. Swartzlander Jr.
    Merged Arithmetic for Computing Wavelet Transforms. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:196-201 [Conf]
  29. Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka
    A fast hybrid carry-lookahead/carry-select adder design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:149-152 [Conf]
  30. Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham
    A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:302-305 [Conf]
  31. Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr.
    High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:68-72 [Conf]
  32. Vijay K. Jain, Gibert E. Perez, Earl E. Swartzlander Jr.
    Arithmetic Error Analysis of a new Reciprocal Cell. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:106-109 [Conf]
  33. Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.
    A Comparative Evaluation of Adders Based on Performance and Testability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:314-317 [Conf]
  34. Hyesook Lim, Earl E. Swartzlander Jr.
    An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:644-649 [Conf]
  35. Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.
    Modified Booth Algorihtm for High Radix Multiplication. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:118-121 [Conf]
  36. Michael J. Schulte, Earl E. Swartzlander Jr.
    A coprocessor for accurate and reliable numerical computations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:686-0 [Conf]
  37. Thomas L. Casavant, Chi-Yuan Chin, Wen-Tsuen Chen, Kang G. Shin, Earl E. Swartzlander Jr., Joseph E. Urban
    What Types of Research Papers Should We Be Writing? [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:22-23 [Conf]
  38. José Duato, C. T. Howard Ho, Ferng-Ching Lin, Lionel M. Ni, Earl E. Swartzlander Jr.
    Is It Possible to Fairly Compare Interconnection Networks?. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:16-19 [Conf]
  39. Yuang-Ming Hsu, Earl E. Swartzlander Jr.
    Sorting Networks with Built-In Error Correction. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:379-385 [Conf]
  40. Earl E. Swartzlander Jr.
    Heterogeneous Parallel Computing. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:8-9 [Conf]
  41. Thomas K. Callaway, Earl E. Swartzlander Jr.
    Implementation of Parallel Processors with Wafer Scale Integration. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:268-274 [Conf]
  42. Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.
    Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:977-980 [Conf]
  43. Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.
    Fault-Tolerant Neural Architectures: The Use of Rotated Operands. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2201-2204 [Conf]
  44. Mohammad S. Khan, Earl E. Swartzlander Jr.
    A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:97-100 [Conf]
  45. Ishaq H. Unwala, Earl E. Swartzlander Jr.
    Superpipelined Adder Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1841-1844 [Conf]
  46. Shaoyun Wang, Earl E. Swartzlander Jr.
    Merged CORDIC Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1988-1991 [Conf]
  47. J. Yoo, E. Lee, Earl E. Swartzlander Jr.
    A self-testing method for the pipelined A/D converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:109-112 [Conf]
  48. Gwangwoo Choe, Earl E. Swartzlander Jr.
    Bipolar merged arithmetic for wavelet architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 1999, pp:462-465 [Conf]
  49. Edwin de Angel, Earl E. Swartzlander Jr.
    Survey of low power techniques for ROMs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:7-11 [Conf]
  50. Earl E. Swartzlander Jr.
    A Review of Large Parallel Counter Designs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:89-98 [Conf]
  51. Earl E. Swartzlander Jr.
    Three Dimensional System on Chip Technology, invited. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:465-470 [Conf]
  52. Earl E. Swartzlander Jr.
    Calculators. [Citation Graph (0, 0)][DBLP]
    IEEE Annals of the History of Computing, 1996, v:18, n:3, pp:70-71 [Journal]
  53. Earl E. Swartzlander Jr.
    Calculators. [Citation Graph (0, 0)][DBLP]
    IEEE Annals of the History of Computing, 1996, v:18, n:4, pp:62-64 [Journal]
  54. Earl E. Swartzlander Jr.
    Calculators. [Citation Graph (0, 0)][DBLP]
    IEEE Annals of the History of Computing, 1997, v:19, n:1, pp:74-75 [Journal]
  55. Earl E. Swartzlander Jr.
    Calculators. [Citation Graph (0, 0)][DBLP]
    IEEE Annals of the History of Computing, 1998, v:20, n:1, pp:67-76 [Journal]
  56. Earl E. Swartzlander Jr.
    Calculators. [Citation Graph (0, 0)][DBLP]
    IEEE Annals of the History of Computing, 1998, v:20, n:3, pp:72-73 [Journal]
  57. W. Kent Fuchs, Earl E. Swartzlander Jr.
    Wafer-Scale Integration: Architectures and Algorithms - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:4, pp:6-8 [Journal]
  58. Earl E. Swartzlander Jr.
    VLSI, MCM, and WSI: A Design Comparison. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:3, pp:28-34 [Journal]
  59. W. Lynn Gallagher, Earl E. Swartzlander Jr.
    Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:6, pp:588-595 [Journal]
  60. Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.
    A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:12, pp:1297-1309 [Journal]
  61. Francescomaria Marino, Earl E. Swartzlander Jr.
    Parallel Implementation of Multidimensional Transforms without Interprocessor Communication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:951-961 [Journal]
  62. Thomas Lynch, Earl E. Swartzlander Jr.
    A Spanning Tree Carry Lookahead Adder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:8, pp:931-939 [Journal]
  63. Michael J. Schulte, Earl E. Swartzlander Jr.
    A Family of Variable-Precision Interval Arithmetic Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:5, pp:387-397 [Journal]
  64. Michael J. Schulte, Earl E. Swartzlander Jr.
    Hardware Designs for Exactly Rounded Elemantary Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:8, pp:964-973 [Journal]
  65. Earl E. Swartzlander Jr.
    Microprogrammed Control for Specialized Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:12, pp:930-934 [Journal]
  66. Earl E. Swartzlander Jr.
    Comment on ``The Focus Number System''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:9, pp:693- [Journal]
  67. Earl E. Swartzlander Jr.
    Merged Arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:10, pp:946-950 [Journal]
  68. Earl E. Swartzlander Jr., Aristides G. Alexopoulos
    The Sign/Logarithm Number System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:12, pp:1238-1242 [Journal]
  69. Earl E. Swartzlander Jr., D. V. Satish Chandra, H. Troy Nagle Jr., Scott A. Starks
    Sign/Logarithm Arithmetic for FFT Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:6, pp:526-534 [Journal]
  70. Earl E. Swartzlander Jr., Barry K. Gilbert
    Arithmetic for Ultra-High-Speed Tomography. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:5, pp:341-353 [Journal]
  71. Earl E. Swartzlander Jr., Barry K. Gilbert
    Supersystems: Technology and Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:5, pp:399-409 [Journal]
  72. Earl E. Swartzlander Jr., Barry K. Gilbert, Irving S. Reed
    Inner Product Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:1, pp:21-31 [Journal]
  73. Earl E. Swartzlander Jr., Douglas J. Heath
    A Routing Algorithm for Signal Processing Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:8, pp:567-572 [Journal]
  74. Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr.
    Hybrid CORDIC Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:11, pp:1202-1207 [Journal]
  75. Sungwook Yu, Earl E. Swartzlander Jr.
    DCT Implementation with Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:9, pp:985-991 [Journal]
  76. Stephen F. Lundstrom, Earl E. Swartzlander Jr.
    Foreword: Advances in Distributed Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1985, v:11, n:10, pp:1092-1096 [Journal]
  77. Heumpil Cho, Earl E. Swartzlander Jr.
    Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:7-15 [Conf]
  78. Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.
    Modified Booth algorithm for high radix fixed-point multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:164-167 [Journal]

  79. Exact rounding of certain elementary functions. [Citation Graph (, )][DBLP]


  80. Estimating the power consumption of CMOS adders. [Citation Graph (, )][DBLP]


  81. A Power-Scalable Switch-Based Multi-processor FFT. [Citation Graph (, )][DBLP]


  82. Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. [Citation Graph (, )][DBLP]


  83. A floating-point fused dot-product unit. [Citation Graph (, )][DBLP]


  84. The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. [Citation Graph (, )][DBLP]


  85. High performance IP lookup circuit using DDR SDRAM. [Citation Graph (, )][DBLP]


  86. 32 bit single cycle nonlinear VLSI cell for the ICA algorithm. [Citation Graph (, )][DBLP]


  87. Optimal initial approximations for the Newton-Raphson division algorithm. [Citation Graph (, )][DBLP]


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