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David T. Blaauw: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aseem Agarwal, Vladimir Zolotov, David T. Blaauw
    Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1243-1260 [Journal]
  2. David T. Blaauw, Luciano Lavagno
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:962-963 [Journal]
  3. David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran
    Slope propagation in static timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1180-1195 [Journal]
  4. Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
    Early probabilistic noise estimation for capacitively coupled interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:337-345 [Journal]
  5. Li Ding 0002, David T. Blaauw, Pinaki Mazumder
    Accurate crosstalk noise modeling for early signal integrity analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:627-634 [Journal]
  6. Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
    Fast on-chip inductance simulation using a precorrected-FFT method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:49-66 [Journal]
  7. Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul
    Probabilistic analysis of interconnect coupling noise. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1188-1203 [Journal]
  8. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
    Hierarchical analysis of power distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:159-168 [Journal]
  9. Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner
    The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1239-1252 [Journal]

  10. Derivation of signal flow for switch-level simulation. [Citation Graph (, )][DBLP]


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