The SCEAS System
| |||||||

## Search the dblp DataBase
Kiamal Z. Pekmestzi:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- E. Chaniotakis, P. Kalivas, Kiamal Z. Pekmestzi
**Long Number Bit-Serial Squarers.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 2005, pp:29-36 [Conf] - George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas
**Hardware compilation using attribute grammars.**[Citation Graph (0, 0)][DBLP] CHARME, 1997, pp:273-290 [Conf] - Kostas Marinis, Nikos K. Moshopoulos, Fotis Karoubalis, Kiamal Z. Pekmestzi
**On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms.**[Citation Graph (0, 0)][DBLP] ISC, 2001, pp:248-265 [Conf] - Nikos K. Moshopoulos, Kiamal Z. Pekmestzi
**A Novel Systolic Architecture for Efficient RSA Implementation.**[Citation Graph (0, 0)][DBLP] Public Key Cryptography, 2001, pp:416-421 [Conf] - Osama Al-Khaleel, Christos A. Papachristou, Frank Wolff, Kiamal Z. Pekmestzi
**A Large Scale Adaptable Multiplier for Cryptographic Applications.**[Citation Graph (0, 0)][DBLP] AHS, 2006, pp:477-484 [Conf] - Kiamal Z. Pekmestzi, Nikos K. Moshopoulos
**A bit-interleaved systolic architecture for a high-speed RSA system.**[Citation Graph (0, 0)][DBLP] Integration, 2001, v:30, n:2, pp:169-175 [Journal] - Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi
**An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding.**[Citation Graph (0, 0)][DBLP] IOLTS, 2007, pp:71-78 [Conf] - P. Bougas, A. Tsirikos, K. Anagnostopoulos, I. Sideris, Kiamal Z. Pekmestzi
**Segmentation based design of serial parallel multipliers.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
**Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme.**[Citation Graph (0, 0)][DBLP] ICSAMOS, 2007, pp:137-144 [Conf] **A high-speed radix-4 multiplexer-based array multiplier.**[Citation Graph (, )][DBLP]**FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.**[Citation Graph (, )][DBLP]**A BISR Architecture for Embedded Memories.**[Citation Graph (, )][DBLP]**A hardware peripheral for Java bytecodes translation acceleration.**[Citation Graph (, )][DBLP]**A fast multiplier-less edge detection accelerator for FPGAs.**[Citation Graph (, )][DBLP]**An instruction set extension for java bytecodes translation acceleration.**[Citation Graph (, )][DBLP]**A Reconfigurable Arithmetic Data-path Based On Regular Interconnection.**[Citation Graph (, )][DBLP]
Search in 0.003secs, Finished in 0.003secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |