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Publications of Author

1. David Harris, Ram Krishnamurthy, Mark Anders, Sanu Mathew, Steven Hsu
   An Improved Unified Scalable Radix-2 Montgomery Multiplier. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2005, pp:172-178 [Conf]
   
2. Vojin G. Oklobdzija, Ram Krishnamurthy
   Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2003, pp:280- [Conf]
   
3. Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
   Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2003, pp:272-279 [Conf]
   
4. Ram Krishnamurthy, Mark Anders, K. Soumyanath, Shekhar Borkar
   Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:43-44 [Conf]
   
5. Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
   Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2005, pp:100-105 [Conf]
   
6. Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar
   A low-leakage dynamic multi-ported register file in 0.13mm CMOS. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2001, pp:68-71 [Conf]
   
7. Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
   Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:122-127 [Conf]
   
8. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
   A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:248-251 [Conf]
   
9. Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar
   An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2005, pp:103-106 [Conf]
   
10. Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
    Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:194-199 [Conf]
    
11. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:415-420 [Conf]
    
12. Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai
    Dynamic addressing memory arrays with physical locality. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:161-170 [Conf]
    
13. Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
    Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1225-1238 [Journal]
    
14. Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
    Comparison of high-performance VLSI adders in the energy-delay space. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:754-758 [Journal]
    
15. Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
    A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:646-649 [Journal]
    
16. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:801-809 [Journal]
    
17. 
    A robust alternate repeater technique for high performance busses in the multi-core era. [Citation Graph (, )][DBLP]
    
    
18. 
    A robust edge encoding technique for energy-efficient multi-cycle interconnect. [Citation Graph (, )][DBLP]
    
    
19. 
    A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. [Citation Graph (, )][DBLP]
    
    
20. 
    A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. [Citation Graph (, )][DBLP]
    
    
21. 
    High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors. [Citation Graph (, )][DBLP]