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Sorin Cotofana: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sorin Cotofana, Casper Lageweg, Stamatis Vassiliadis
    On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2003, pp:245-252 [Conf]
  2. Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, A. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio
    CONAN - A Design Exploration Framework for Reliable Nano-Electronics. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:260-267 [Conf]
  3. Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
    Binary Multiplication based on Single Electron Tunneling. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:152-166 [Conf]
  4. Cor Meenderinck, Sorin Cotofana, Casper Lageweg
    High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:294-302 [Conf]
  5. Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven
    Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:250-259 [Conf]
  6. Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
    Efficient Hardware for Antialiasing Coverage Mask Generation. [Citation Graph (0, 0)][DBLP]
    Computer Graphics International, 2004, pp:257-264 [Conf]
  7. Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
    GRAAL - A Development Framework for Embedded Graphics Accelerators. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1366-1367 [Conf]
  8. Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven
    Compositional Memory Systems for Data Intensive Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:728-729 [Conf]
  9. Tudor Niculiu, Chouki Aktouf, Sorin Cotofana
    Hierarchical interfaces for hardware software systems. [Citation Graph (0, 0)][DBLP]
    ESM, 2000, pp:647-654 [Conf]
  10. Tudor Niculiu, Sorin Cotofana
    Hierarchical Intellignet Mixed Simulation. [Citation Graph (0, 0)][DBLP]
    ESM, 2002, pp:159-162 [Conf]
  11. Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis
    Counter Based Superscalar Instruction Issuing. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1307-1315 [Conf]
  12. Sorin Cotofana, Stamatis Vassiliadis
    On the Design Complexity of the Issue Logic of Superscalar Machines. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10277-10284 [Conf]
  13. Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
    A Sum of Absolute Differences Implementation in FPGA Hardware. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2002, pp:183-188 [Conf]
  14. Marian Stanca, Stamatis Vassiliadis, Sorin Cotofana, Henk Corporaal
    Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:965-968 [Conf]
  15. Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis
    Vector ISA Extension for Sparse Matrix-Vector Multiplication. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:708-715 [Conf]
  16. Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana
    Topic 15+20: Multimedia and Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:651-652 [Conf]
  17. Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
    MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:261-0 [Conf]
  18. Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers
    Field-Programmable Custom Computing Machines - A Taxonomy -. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:79-88 [Conf]
  19. Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana
    The MOLEN rho-mu-Coded Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:275-285 [Conf]
  20. Sorin Cotofana, Stamatis Vassiliadis
    Serial Binary Addition with Polynominally Bounded Weights. [Citation Graph (0, 0)][DBLP]
    ICANN, 1996, pp:741-746 [Conf]
  21. Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
    MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:425-430 [Conf]
  22. Tudor Niculiu, Cristian Lupu, Sorin Cotofana
    Consciousness for modeling intelligence - simulating the evolution by closure to the inverse. [Citation Graph (0, 0)][DBLP]
    ICINCO-ICSO, 2006, pp:187-190 [Conf]
  23. Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
    Multimedia Enhanced General-Purpose Processors. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (III), 2000, pp:1493-1496 [Conf]
  24. Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana
    A Hierarchical Sparse Matrix Storage Format for Vector Processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:61- [Conf]
  25. Marius Padure, Sorin Cotofana, Stamatis Vassiliadis
    Design and experimental results of a CMOS flip-flop featuring embedded threshold logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:253-256 [Conf]
  26. Dan Crisu, Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha
    Low cost and latency embedded 3D graphics reciprocation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:905-908 [Conf]
  27. Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis
    Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:127-134 [Conf]
  28. Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
    General-Purpose Processor Huffman Encoding Extension. [Citation Graph (0, 0)][DBLP]
    ITCC, 2000, pp:158-163 [Conf]
  29. Peter Celinski, Sorin Cotofana, Derek Abbott
    A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 2003, pp:73-80 [Conf]
  30. Marius Padure, Sorin Cotofana, Stamatis Vassiliadis
    CMOS Implementation of Generalized Threshold Functions. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 2003, pp:65-72 [Conf]
  31. Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana
    D-SAB: A Sparse Matrix Benchmark Suite. [Citation Graph (0, 0)][DBLP]
    PaCT, 2003, pp:549-554 [Conf]
  32. Peter Celinski, Derek Abbott, Sorin Cotofana
    Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:899-906 [Conf]
  33. Cor Meenderinck, Sorin Cotofana
    High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:447-456 [Conf]
  34. Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
    High-Level Energy Estimation for ARM-Based SOCs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:168-177 [Conf]
  35. Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
    A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:224-241 [Conf]
  36. Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
    Microcoded Reconfigurable Embedded Processors: Current Developments. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:207-223 [Conf]
  37. Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
    Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:258-262 [Conf]
  38. Sorin Cotofana, Stamatis Vassiliadis
    Serial binary multiplication with feed-forward neural networks. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1999, v:28, n:1-3, pp:1-19 [Journal]
  39. Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana
    Microcode Processing: Positioning and Directions. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:4, pp:21-31 [Journal]
  40. Sorin Cotofana, Stamatis Vassiliadis
    Signed Digit Addition and Related Operations with Threshold Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:3, pp:193-207 [Journal]
  41. Stamatis Vassiliadis, Sorin Cotofana, Koen Bertels
    2-1 Additions and Related Arithmetic Operations with Threshold Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:9, pp:1062-1067 [Journal]
  42. Cor Meenderinck, Sorin Cotofana
    Electron counting based high-radix multiplication in single electron tunneling technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  43. Coarse Reconfigurable Multimedia Unit Extension. [Citation Graph (, )][DBLP]


  44. Can SG-FET Replace FET in Sleep Mode Circuits? [Citation Graph (, )][DBLP]


  45. Emerging non-CMOS nanoelectronic devices - What are they?. [Citation Graph (, )][DBLP]


  46. GRAAL: A Framework for Low-Power 3D Graphics Accelerators. [Citation Graph (, )][DBLP]


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