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Publications of Author

1. Marco Macchetti, Luigi Dadda
   Quasi-Pipelined Hash Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2005, pp:222-229 [Conf]
   
2. Luca Breveglieri, Alessandra Cherubini, Marco Macchetti
   On the Generalized Linear Equivalence of Functions Over Finite Fields. [Citation Graph (0, 0)][DBLP]
   ASIACRYPT, 2004, pp:79-91 [Conf]
   
3. Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Stefano Marchesin
   Efficient Software Implementation of AES on 32-Bit Platforms. [Citation Graph (0, 0)][DBLP]
   CHES, 2002, pp:159-171 [Conf]
   
4. Luigi Dadda, Marco Macchetti, Jeff Owen
   The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512). [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:70-75 [Conf]
   
5. Guido Bertoni, Marco Macchetti, Luca Negri, Pasqualina Fragneto
   Power-efficient ASIC synthesis of cryptographic sboxes. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:277-281 [Conf]
   
6. Luigi Dadda, Marco Macchetti, Jeff Owen
   An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512). [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:421-425 [Conf]
   
7. Marco Macchetti, Mario Caironi, Luca Breveglieri, Alessandra Cherubini
   A Complete Formulation of Generalized Affine Equivalence. [Citation Graph (0, 0)][DBLP]
   ICTCS, 2005, pp:338-347 [Conf]
   
8. Guido Bertoni, A. Bircan, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Vittorio Zaccaria
   About the performances of the Advanced Encryption Standard in embedded systems with cache memory. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:145-148 [Conf]
   
9. Kubilay Atasu, Luca Breveglieri, Marco Macchetti
   Efficient AES implementations for ARM based platforms. [Citation Graph (0, 0)][DBLP]
   SAC, 2004, pp:841-845 [Conf]
   
10. Matteo Giaconia, Marco Macchetti, Francesco Regazzoni, Kai Schramm
    Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:731-737 [Conf]
    
11. Marco Macchetti, Wenyu Chen
    ASIC hardware implementation of the IDEA NXT encryption algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
12. Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
    A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:209-214 [Conf]
    
13. 
    Revisiting the IDEA Philosophy. [Citation Graph (, )][DBLP]
    
    
14. 
    A Memory Unit for Priority Management in IPSec Accelerators. [Citation Graph (, )][DBLP]