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Vojin G. Oklobdzija :
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Charles U. Martel , Vojin G. Oklobdzija , R. Ravi , Paul F. Stelling Design Strategies for Optimal Multiplier Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 1995, pp:42-49 [Conf ] Vojin G. Oklobdzija , Ram Krishnamurthy Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 2003, pp:280- [Conf ] Vojin G. Oklobdzija , Bart R. Zeydel , Hoang Q. Dao , Sanu Mathew , Ram Krishnamurthy Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 2003, pp:272-279 [Conf ] Paul F. Stelling , Vojin G. Oklobdzija Implementing Multiply-Accumulate Operation in Multiplication Time. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 1997, pp:99-0 [Conf ] Bart R. Zeydel , Theo T. J. H. Kluter , Vojin G. Oklobdzija Efficient Mapping of Addition Recurrence Algorithms in CMOS. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 2005, pp:107-113 [Conf ] Aamir A. Farooqui , Vojin G. Oklobdzija VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1999, pp:30-33 [Conf ] Vojin G. Oklobdzija High-Performance Computer Arithmetic and Implementations: Introduction. [Citation Graph (0, 0)][DBLP ] HICSS (1), 1994, pp:280-281 [Conf ] Hoang Q. Dao , Bart R. Zeydel , Vojin G. Oklobdzija Architectural Considerations for Energy Efficiency. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:13-16 [Conf ] Rupinder Hundal , Vojin G. Oklobdzija Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination. [Citation Graph (0, 0)][DBLP ] ICCD, 1994, pp:60-64 [Conf ] Nikola Nedovic , Marko Aleksic , Vojin G. Oklobdzija Timing Characterization of Dual-edge Triggered Flip-flops. [Citation Graph (0, 0)][DBLP ] ICCD, 2001, pp:538-541 [Conf ] Nikola Nedovic , Vojin G. Oklobdzija Dynamic Flip-Flop with Improved Power. [Citation Graph (0, 0)][DBLP ] ICCD, 2000, pp:323-0 [Conf ] Milena Vratonjic , Bart R. Zeydel , Vojin G. Oklobdzija Low- and Ultra Low-Power Arithmetic Units: Design and Comparison. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:249-252 [Conf ] K. J. Runge , L. P. Lee , J. Correa , R. T. Scalettar , Vojin G. Oklobdzija Monte Carlo and molecular dynamics simulations using p4. [Citation Graph (0, 0)][DBLP ] IPPS, 1995, pp:53-59 [Conf ] Aamir A. Farooqui , Vojin G. Oklobdzija , Sadiq M. Sait Area-time optimal adder with relative placement generator. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:141-144 [Conf ] Xiao Yan Yu , Vojin G. Oklobdzija , William W. Walker An efficient transistor optimizer for custom circuits. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:197-200 [Conf ] Nikola Nedovic , Marko Aleksic , Vojin G. Oklobdzija Comparative analysis of double-edge versus single-edge triggered clocked storage elements. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2002, pp:105-108 [Conf ] Hoang Q. Dao , Kevin J. Nowka , Vojin G. Oklobdzija Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation. [Citation Graph (0, 0)][DBLP ] ISLPED, 2001, pp:56-59 [Conf ] Dragan Maksimovic , Vojin G. Oklobdzija , Borivoje Nikolic , K. Wayne Current Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. [Citation Graph (0, 0)][DBLP ] ISLPED, 1997, pp:323-327 [Conf ] Nikola Nedovic , Marko Aleksic , Vojin G. Oklobdzija Conditional pre-charge techniques for power-efficient dual-edge clocking. [Citation Graph (0, 0)][DBLP ] ISLPED, 2002, pp:56-59 [Conf ] Vojin G. Oklobdzija , Jens Sparsø Future directions in clocking multi-ghz systems. [Citation Graph (0, 0)][DBLP ] ISLPED, 2002, pp:219- [Conf ] Vladimir Stojanovic , Vojin G. Oklobdzija , Raminder Singh Bajwa A unified approach in the analysis of latches and flip-flops for low-power systems. [Citation Graph (0, 0)][DBLP ] ISLPED, 1998, pp:227-232 [Conf ] K. Wayne Current , Vojin G. Oklobdzija , Dragan Maksimovic Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:86-0 [Conf ] Martin Saint-Laurent , Vojin G. Oklobdzija , Simon S. Singh , Madhavan Swaminathan Optimal Sequencing Energy Allocation for CMOS Integrated Systems. [Citation Graph (0, 0)][DBLP ] ISQED, 2002, pp:194-199 [Conf ] J. Paul Roth , Vojin G. Oklobdzija , John F. Beetem Test Generation for FET Switching Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1984, pp:59-62 [Conf ] Marko Aleksic , Nikola Nedovic , K. Wayne Current , Vojin G. Oklobdzija A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. [Citation Graph (0, 0)][DBLP ] PATMOS, 2005, pp:724-732 [Conf ] Christophe Giacomotto , Nikola Nedovic , Vojin G. Oklobdzija Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. [Citation Graph (0, 0)][DBLP ] PATMOS, 2006, pp:360-369 [Conf ] Hoang Q. Dao , Vojin G. Oklobdzija Performance Comparison of VLSI Adders Using Logical Effort. [Citation Graph (0, 0)][DBLP ] PATMOS, 2002, pp:25-34 [Conf ] Hoang Q. Dao , Bart R. Zeydel , Vojin G. Oklobdzija Energy Optimization of High-Performance Circuits. [Citation Graph (0, 0)][DBLP ] PATMOS, 2003, pp:399-408 [Conf ] Vojin G. Oklobdzija Clocking and Clocked Storage Elements in Multi-GHz Environment. [Citation Graph (0, 0)][DBLP ] PATMOS, 2002, pp:128-145 [Conf ] Milena Vratonjic , Bart R. Zeydel , Vojin G. Oklobdzija Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. [Citation Graph (0, 0)][DBLP ] PATMOS, 2006, pp:148-156 [Conf ] Xiao Yan Yu , Robert K. Montoye , Kevin J. Nowka , Bart R. Zeydel , Vojin G. Oklobdzija Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. [Citation Graph (0, 0)][DBLP ] PATMOS, 2006, pp:47-55 [Conf ] Bart R. Zeydel , Vojin G. Oklobdzija Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations. [Citation Graph (0, 0)][DBLP ] PATMOS, 2006, pp:127-136 [Conf ] Vojin G. Oklobdzija Clocking and clocked storage elements in a multi-gigahertz environment. [Citation Graph (0, 0)][DBLP ] IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:567-584 [Journal ] Vojin G. Oklobdzija , Earl R. Barnes On Implementing Addition in VLSI Technology. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 1988, v:5, n:6, pp:716-728 [Journal ] Pak K. Chan , Martine D. F. Schlag , Clark D. Thomborson , Vojin G. Oklobdzija Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1992, v:41, n:8, pp:920-930 [Journal ] Vojin G. Oklobdzija , Milos D. Ercegovac A On-Line Square Root Algorithm. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1982, v:31, n:1, pp:70-75 [Journal ] Vojin G. Oklobdzija , David Villeger , Simon S. Liu A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:3, pp:294-306 [Journal ] Paul F. Stelling , Charles U. Martel , Vojin G. Oklobdzija , R. Ravi Optimal Circuits for Parallel Multipliers. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:3, pp:273-285 [Journal ] Hoang Q. Dao , Bart R. Zeydel , Vojin G. Oklobdzija Energy optimization of pipelined digital systems using circuit sizing and supply scaling. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:122-134 [Journal ] Nikola Nedovic , Vojin G. Oklobdzija Dual-edge triggered storage elements and clocking strategy for low-power systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:577-590 [Journal ] Vojin G. Oklobdzija , Bart R. Zeydel , Hoang Q. Dao , Sanu Mathew , Ram Krishnamurthy Comparison of high-performance VLSI adders in the energy-delay space. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:754-758 [Journal ] Mandeep Singh , Christophe Giacomotto , Bart R. Zeydel , Vojin G. Oklobdzija Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. [Citation Graph (0, 0)][DBLP ] PATMOS, 2007, pp:181-190 [Conf ] Vojin G. Oklobdzija An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:124-128 [Journal ] Vojin G. Oklobdzija , David Villeger Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:292-301 [Journal ] Dragan Maksimovic , Vojin G. Oklobdzija , Borivoje Nikolic , K. Wayne Current Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:460-463 [Journal ] Energy efficient implementation of parallel CMOS multipliers with improved compressors. [Citation Graph (, )][DBLP ] Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements. [Citation Graph (, )][DBLP ] A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). [Citation Graph (, )][DBLP ] Low-Power Soft Error Hardened Latch. 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