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Florent de Dinechin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Florent de Dinechin, Alexey V. Ershov, Nicolas Gast
    Towards the Post-Ultimate libm. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2005, pp:288-295 [Conf]
  2. Florent de Dinechin, Arnaud Tisserand
    Some Improvements on Multipartite Table Methods . [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:128-135 [Conf]
  3. Jérémie Detrey, Florent de Dinechin
    Table-based polynomials for fast hardware function evaluation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:328-333 [Conf]
  4. Florent de Dinechin
    Libraries of schedule-free operators in Alpha. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:239-0 [Conf]
  5. Florent de Dinechin, Sophie Robert
    Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:381-0 [Conf]
  6. Sylvain Collange, Jérémie Detrey, Florent de Dinechin
    Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:197-203 [Conf]
  7. Florent de Dinechin, Wayne Luk, Steve McKeever
    Towards Adaptable Hierarchical Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:254- [Conf]
  8. Jérémie Detrey, Florent de Dinechin
    Second Order Function Approximation Using a Single Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:221-230 [Conf]
  9. Jérémie Detrey, Florent de Dinechin
    A Parameterized Floating-Point Exponential Function for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:27-34 [Conf]
  10. Jérémie Detrey, Florent de Dinechin
    Multipartite Tables in JBits for the Evaluation of Functions on FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  11. Florent de Dinechin, Doran Wilde, Sanjay V. Rajopadhye, Rumen Andonov
    A Regular VLSI Array for an Irregular Algorithm. [Citation Graph (0, 0)][DBLP]
    IRREGULAR, 1996, pp:195-200 [Conf]
  12. David Defour, Florent de Dinechin
    Software Carry-Save: A Case Study for Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    PaCT, 2003, pp:207-214 [Conf]
  13. Florent de Dinechin, T. Risset, Sophie Robert
    Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms. [Citation Graph (0, 0)][DBLP]
    PARCO, 1997, pp:261-268 [Conf]
  14. Florent de Dinechin, Vincent Lefèvre
    Constant Multipliers for FPGAs. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  15. Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond
    Assisted verification of elementary functions using Gappa. [Citation Graph (0, 0)][DBLP]
    SAC, 2006, pp:1318-1322 [Conf]
  16. Florent de Dinechin
    The Price of Routing in FPGAs. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2000, v:6, n:2, pp:227-239 [Journal]
  17. Florent de Dinechin, Arnaud Tisserand
    Multipartite Table Methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:3, pp:319-330 [Journal]
  18. Jérémie Detrey, Florent de Dinechin, Xavier Pujol
    Return of the hardware floating-point elementary function. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:161-168 [Conf]
  19. Jérémie Detrey, Florent de Dinechin
    Parameterized floating-point logarithm and exponential functions for FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:8, pp:537-545 [Journal]

  20. Integer and floating-point constant multipliers for FPGAs. [Citation Graph (, )][DBLP]

  21. When FPGAs are better at floating-point than microprocessors. [Citation Graph (, )][DBLP]

  22. Floating-Point Trigonometric Functions for FPGAs. [Citation Graph (, )][DBLP]

  23. Generating high-performance custom floating-point pipelines. [Citation Graph (, )][DBLP]

  24. Large multipliers with fewer DSP blocks. [Citation Graph (, )][DBLP]

  25. FPGA-Based Computation of the Inductance of Coils Used for the Magnetic Stimulation of the Nervous System. [Citation Graph (, )][DBLP]

  26. Certifying floating-point implementations using Gappa [Citation Graph (, )][DBLP]

  27. Optimizing polynomials for floating-point implementation [Citation Graph (, )][DBLP]

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