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Publications of Author

1. Silvia M. Müller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong
   The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 2005, pp:59-67 [Conf]
   
2. Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong
   A cycle accurate power estimation tool. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:867-870 [Conf]
   
3. Stephen D. Posluszny, N. Aoki, D. Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
   "Timing closure by design, " a high frequency microprocessor design methodology. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:712-717 [Conf]
   
4. Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman
   The circuit design of the synergistic processor element of a CELL processor. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:111-117 [Conf]
   
5. David Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz
   High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. [Citation Graph (0, 0)][DBLP]
   VTS, 1998, pp:234-238 [Conf]
   
6. David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
   Custom circuit design as a driver of microprocessor performance. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2000, v:44, n:6, pp:799-822 [Journal]
   
7. Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara
   Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2005, v:25, n:5, pp:30-38 [Journal]
   
8. Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman
   Power-Conscious Design of the Cell Processor's Synergistic Processor Element. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2005, v:25, n:5, pp:10-18 [Journal]
   
9. 
   Challenges at 45nm and beyond. [Citation Graph (, )][DBLP]