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## Search the dblp DataBase
Bart R. Zeydel:
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## Publications of Author- Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
**Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 2003, pp:272-279 [Conf] - Bart R. Zeydel, Theo T. J. H. Kluter, Vojin G. Oklobdzija
**Efficient Mapping of Addition Recurrence Algorithms in CMOS.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 2005, pp:107-113 [Conf] - Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
**Architectural Considerations for Energy Efficiency.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:13-16 [Conf] - Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija
**Low- and Ultra Low-Power Arithmetic Units: Design and Comparison.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:249-252 [Conf] - Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
**Energy Optimization of High-Performance Circuits.**[Citation Graph (0, 0)][DBLP] PATMOS, 2003, pp:399-408 [Conf] - Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija
**Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design.**[Citation Graph (0, 0)][DBLP] PATMOS, 2006, pp:148-156 [Conf] - Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija
**Circuit Design Style for Energy Efficiency: LSDL and Compound Domino.**[Citation Graph (0, 0)][DBLP] PATMOS, 2006, pp:47-55 [Conf] - Bart R. Zeydel, Vojin G. Oklobdzija
**Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations.**[Citation Graph (0, 0)][DBLP] PATMOS, 2006, pp:127-136 [Conf] - Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
**Energy optimization of pipelined digital systems using circuit sizing and supply scaling.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:122-134 [Journal] - Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
**Comparison of high-performance VLSI adders in the energy-delay space.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:754-758 [Journal] - Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija
**Logic Style Comparison for Ultra Low Power Operation in 65nm Technology.**[Citation Graph (0, 0)][DBLP] PATMOS, 2007, pp:181-190 [Conf]
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