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Title:
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Robert Michael Owens: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin
    Reducing the number of counters needed for integer multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:38-41 [Conf]
  2. Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga
    Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:65-71 [Conf]
  3. Kevin P. Acken, Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
    An Architectural Design For Parallel Fractal Compression. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:3-11 [Conf]
  4. Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
    The MGAP's programming environment and the *C++ language. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:121-124 [Conf]
  5. Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
    Motion Estimation Algorithms on Fine Grain Array Processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:204-213 [Conf]
  6. Mohan Vishwanath, Robert Michael Owens
    A Common Architecture For The DWT and IDWT. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:193-198 [Conf]
  7. J. A. Beekman, Robert Michael Owens, Mary Jane Irwin
    Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:357-362 [Conf]
  8. Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa
    Validation of an Architectural Level Power Analysis Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:242-245 [Conf]
  9. Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin
    DECOMPOSER: A Synthesizer for Systolic Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:650-653 [Conf]
  10. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
    Multi-Level Logic Synthesis Using Communication Complexity. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:215-220 [Conf]
  11. Mary Jane Irwin, Robert Michael Owens
    A Comparison of Four Two-dimensional Gate Matrix Layout Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:698-701 [Conf]
  12. Soohong Kim, Robert Michael Owens, Mary Jane Irwin
    Experiments with a Performance Driven Module Generator. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:687-690 [Conf]
  13. Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    Accurate Estimation of Combinational Circuit Activity. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:618-622 [Conf]
  14. Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
    Energy Characterization based on Clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:702-707 [Conf]
  15. Robert Michael Owens, Mary Jane Irwin
    An Overview of the Penn State Design System. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:516-522 [Conf]
  16. Kevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
    The MGAP Family of Processor Arrays. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:105-0 [Conf]
  17. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    Fast algorithm for performance-oriented Steiner routing. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:198-203 [Conf]
  18. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    Recent Developments in Performance Driven Steiner Routing: An Overview. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:137-142 [Conf]
  19. Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin
    A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:182-0 [Conf]
  20. Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
    Some Issues in Gray Code Addressing. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:178-181 [Conf]
  21. Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
    The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:96-104 [Conf]
  22. Robert Michael Owens, Joseph JáJá
    Optimal Algorithms for Mesh-Connected Parallel Processors with Serial Memories. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:812-818 [Conf]
  23. Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
    Image Processing with the MGAP: A Cost Effective Solution. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:439-443 [Conf]
  24. Benjamin Bishop, Robert Michael Owens, Mary Jane Irwin
    Aggressive Dynamic Execution of Multimedia Kernel Traces. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:640-646 [Conf]
  25. Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens, Chen-Mi Wu
    Dynamic Space Warping Algorithms on Fine-Graln Array Processors. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:921-925 [Conf]
  26. Robert Michael Owens, Mary Jane Irwin
    On-Line Algorithms for the Design of Pipeline Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1979, pp:12-19 [Conf]
  27. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    High-throughput and low-power DSP using clocked-CMOS circuitry. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:139-144 [Conf]
  28. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:167-172 [Conf]
  29. Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens
    Power comparisons for barrel shifters. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:209-212 [Conf]
  30. Patrick Hicks, Matthew Walnock, Robert Michael Owens
    Analysis of power consumption in memory hierarchies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:239-242 [Conf]
  31. Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin, Rita Yu Chen, Debashree Ghosh
    Techniques for low energy software. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:72-75 [Conf]
  32. Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
    Unifying carry-sum and signed-digital number representations for low power. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:15-20 [Conf]
  33. Mary Sue Haydt, Robert Michael Owens, Samiha Mourad
    Modeling the Effect of Ground Bounce on Noise Margin. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:279-285 [Conf]
  34. Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
    A Massively Parallel, Micro-Grained VLSI Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:250-255 [Conf]
  35. Manjit Borah, Mary Jane Irwin, Robert Michael Owens
    Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:294-298 [Conf]
  36. Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
    A Simulation Methodology for Software Energy Evaluation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:509-510 [Conf]
  37. Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
    Design tradeoffs in high speed multipliers and FIR filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:29-32 [Conf]
  38. Mary Jane Irwin, Robert Michael Owens
    Digit-Pipelined Arithmetic as Illustrated By the Paste-Up System: A Tutorial. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1987, v:20, n:4, pp:61-73 [Journal]
  39. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    A Fast and Simple Steiner Routing Heuristic. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1999, v:90, n:1-3, pp:51-67 [Journal]
  40. Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin
    Digit Serial Multipliers. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:11, n:2, pp:156-162 [Journal]
  41. Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
    Motion Analysis on the Micro Grained Array Processor. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1997, v:3, n:2, pp:101-110 [Journal]
  42. Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
    Area Time Trade-Offs in Micro-Grain VLSI Array Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:10, pp:1121-1128 [Journal]
  43. Mary Jane Irwin, Robert Michael Owens
    Fully Digit On-Line Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:4, pp:402-406 [Journal]
  44. Mary Jane Irwin, Robert Michael Owens
    A Two-Dimensional, Distributed Logic Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:10, pp:1094-1101 [Journal]
  45. Joseph JáJá, Robert Michael Owens
    VLSI Sorting with Reduced Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:7, pp:668-671 [Journal]
  46. Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang
    ELM-A Fast Addition Algorithm Discovered by a Program. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:9, pp:1181-1184 [Journal]
  47. Gueesang Lee, Mary Jane Irwin, Robert Michael Owens
    Polynomial Time Testability of Circuits Generated by Input Decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:2, pp:201-210 [Journal]
  48. Robert Michael Owens
    Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:4, pp:406-411 [Journal]
  49. Robert Michael Owens, Mary Jane Irwin
    The Arithmetic Cube. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:11, pp:1342-1348 [Journal]
  50. Robert Michael Owens, Mary Jane Irwin
    Being Stingy with Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:6, pp:809-818 [Journal]
  51. Robert Michael Owens, Joseph JáJá
    Parallel Sorting with Serial Momories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:4, pp:379-383 [Journal]
  52. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    An edge-based heuristic for Steiner routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1563-1568 [Journal]
  53. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    Transistor sizing for low power CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:665-671 [Journal]
  54. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
    A fast algorithm for minimizing the Elmore delay to identified critical sinks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:753-759 [Journal]
  55. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
    Exploiting communication complexity for multilevel logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1017-1027 [Journal]
  56. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
    Efficiently computing communication complexity for multilevel logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:545-554 [Journal]
  57. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang
    Logic synthesis for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1280-1287 [Journal]
  58. Robert Michael Owens, Mary Jane Irwin
    A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:420-428 [Journal]
  59. Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, W.-L. Yang
    The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:491-502 [Journal]
  60. Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
    Power-delay characteristics of CMOS adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:377-381 [Journal]
  61. Gayles Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
    The design of the MGAP-2: a micro-grained massively parallel array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:709-716 [Journal]

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