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## Search the dblp DataBase
Vassilis Paliouras:
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## Publications of Author- Vassilis Paliouras, Thanos Stouraitis
**Low-Power Properties of the Logarithmic Number System.**[Citation Graph (0, 0)][DBLP] IEEE Symposium on Computer Arithmetic, 2001, pp:229-236 [Conf] - Vassilis Paliouras, Thanos Stouraitis
**Area-time performance of VLSI FIR filter architectures based on residue arithmetic.**[Citation Graph (0, 0)][DBLP] EUROMICRO, 1997, pp:576-583 [Conf] - Vassilis Paliouras, Alexander Skavantzos, Thanos Stouraitis
**Multi-voltage low power convolvers using the polynomial residue number system.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2002, pp:7-11 [Conf] - E. Fotopoulou, Vassilis Paliouras, Thanos Stouraitis
**A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems.**[Citation Graph (0, 0)][DBLP] ISCAS (2), 2003, pp:125-128 [Conf] - Theodoros Giannopoulos, Vassilis Paliouras
**An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:85-88 [Conf] - I. Kouretas, Vassilis Paliouras
**High-radix redundant circuits for RNS modulo r**[Citation Graph (0, 0)][DBLP]^{n}-1, r^{n}, or r^{n}+1. ISCAS (5), 2003, pp:229-232 [Conf] - Stamatis Krommydas, Vassilis Paliouras
**An efficient memory compression scheme for 8 k FFT in a DVB-T receiver and the corresponding error model.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:89-92 [Conf] - I. Orginos, Vassilis Paliouras, Thanos Stouraitis
**A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:1992-1995 [Conf] - Vassilis Paliouras, Thanos Stouraitis
**Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors.**[Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:79-82 [Conf] - Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis
**Methodology for the Design of Signed-digit DSP Processors.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1833-1836 [Conf] - Vassilis Paliouras, Thanos Stouraitis
**Signal activity and power consumption reduction using the logarithmic number system.**[Citation Graph (0, 0)][DBLP] ISCAS (2), 2001, pp:653-656 [Conf] - Vassilis Paliouras, Thanos Stouraitis
**Novel high-radix residue number system multipliers and adders.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:451-454 [Conf] - Theodoros Giannopoulos, Vassilis Paliouras
**Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction.**[Citation Graph (0, 0)][DBLP] PATMOS, 2005, pp:177-186 [Conf] - Theodoros Giannopoulos, Vassilis Paliouras
**Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters.**[Citation Graph (0, 0)][DBLP] PATMOS, 2006, pp:203-213 [Conf] - Konstantina Karagianni, Vassilis Paliouras
**Low-Power Aspects of Nonlinear Signal Processing.**[Citation Graph (0, 0)][DBLP] PATMOS, 2005, pp:518-527 [Conf] - Vassilis Paliouras, Thanos Stouraitis
**Logarithmic Number System for Low-Power Arithmetic.**[Citation Graph (0, 0)][DBLP] PATMOS, 2000, pp:285-294 [Conf] - P. Vouzis, Vassilis Paliouras
**Optimal Logarithmic Representation in Terms of SNR Behavior.**[Citation Graph (0, 0)][DBLP] PATMOS, 2004, pp:760-769 [Conf] - Konstantina Karagianni, Vassilis Paliouras, George Diamantakos, Thanos Stouraitis
**Operation-Saving VLSI Architectures for 3D Geometrical Transformations.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2001, v:50, n:6, pp:609-622 [Journal] - Theodoros Giannopoulos, Vassilis Paliouras
**A novel technique for low-power D/A conversion based on PAPR reduction.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Ch. Basetas, I. Kouretas, Vassilis Paliouras
**Low-Power Digital Filtering Based on the Logarithmic Number System.**[Citation Graph (0, 0)][DBLP] PATMOS, 2007, pp:546-555 [Conf] - Johan Vounckx, Vassilis Paliouras
**Editorial.**[Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2006, v:2, n:1, pp:- [Journal] **Variation-tolerant Design Using Residue Number System.**[Citation Graph (, )][DBLP]**Using CLNS for FFTs in OFDM demodulation of UWB receivers.**[Citation Graph (, )][DBLP]**Low-power logarithmic number system addition/subtraction and their impact on digital filters.**[Citation Graph (, )][DBLP]**Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication.**[Citation Graph (, )][DBLP]**Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units.**[Citation Graph (, )][DBLP]**On The Complexity of Joint Demodulation and Convolutional Decoding.**[Citation Graph (, )][DBLP]**Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding.**[Citation Graph (, )][DBLP]**Simplified Criteria for Early Iterative Decoding Termination.**[Citation Graph (, )][DBLP]**Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems.**[Citation Graph (, )][DBLP]**A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information.**[Citation Graph (, )][DBLP]
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