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Vassilis Paliouras: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vassilis Paliouras, Thanos Stouraitis
    Low-Power Properties of the Logarithmic Number System. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:229-236 [Conf]
  2. Vassilis Paliouras, Thanos Stouraitis
    Area-time performance of VLSI FIR filter architectures based on residue arithmetic. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:576-583 [Conf]
  3. Vassilis Paliouras, Alexander Skavantzos, Thanos Stouraitis
    Multi-voltage low power convolvers using the polynomial residue number system. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:7-11 [Conf]
  4. E. Fotopoulou, Vassilis Paliouras, Thanos Stouraitis
    A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:125-128 [Conf]
  5. Theodoros Giannopoulos, Vassilis Paliouras
    An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:85-88 [Conf]
  6. I. Kouretas, Vassilis Paliouras
    High-radix redundant circuits for RNS modulo rn-1, rn, or rn+1. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:229-232 [Conf]
  7. Stamatis Krommydas, Vassilis Paliouras
    An efficient memory compression scheme for 8 k FFT in a DVB-T receiver and the corresponding error model. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:89-92 [Conf]
  8. I. Orginos, Vassilis Paliouras, Thanos Stouraitis
    A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1992-1995 [Conf]
  9. Vassilis Paliouras, Thanos Stouraitis
    Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:79-82 [Conf]
  10. Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis
    Methodology for the Design of Signed-digit DSP Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1833-1836 [Conf]
  11. Vassilis Paliouras, Thanos Stouraitis
    Signal activity and power consumption reduction using the logarithmic number system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:653-656 [Conf]
  12. Vassilis Paliouras, Thanos Stouraitis
    Novel high-radix residue number system multipliers and adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:451-454 [Conf]
  13. Theodoros Giannopoulos, Vassilis Paliouras
    Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:177-186 [Conf]
  14. Theodoros Giannopoulos, Vassilis Paliouras
    Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:203-213 [Conf]
  15. Konstantina Karagianni, Vassilis Paliouras
    Low-Power Aspects of Nonlinear Signal Processing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:518-527 [Conf]
  16. Vassilis Paliouras, Thanos Stouraitis
    Logarithmic Number System for Low-Power Arithmetic. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:285-294 [Conf]
  17. P. Vouzis, Vassilis Paliouras
    Optimal Logarithmic Representation in Terms of SNR Behavior. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:760-769 [Conf]
  18. Konstantina Karagianni, Vassilis Paliouras, George Diamantakos, Thanos Stouraitis
    Operation-Saving VLSI Architectures for 3D Geometrical Transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:6, pp:609-622 [Journal]
  19. Theodoros Giannopoulos, Vassilis Paliouras
    A novel technique for low-power D/A conversion based on PAPR reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  20. Ch. Basetas, I. Kouretas, Vassilis Paliouras
    Low-Power Digital Filtering Based on the Logarithmic Number System. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:546-555 [Conf]
  21. Johan Vounckx, Vassilis Paliouras
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:- [Journal]

  22. Variation-tolerant Design Using Residue Number System. [Citation Graph (, )][DBLP]

  23. Using CLNS for FFTs in OFDM demodulation of UWB receivers. [Citation Graph (, )][DBLP]

  24. Low-power logarithmic number system addition/subtraction and their impact on digital filters. [Citation Graph (, )][DBLP]

  25. Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication. [Citation Graph (, )][DBLP]

  26. Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units. [Citation Graph (, )][DBLP]

  27. On The Complexity of Joint Demodulation and Convolutional Decoding. [Citation Graph (, )][DBLP]

  28. Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding. [Citation Graph (, )][DBLP]

  29. Simplified Criteria for Early Iterative Decoding Termination. [Citation Graph (, )][DBLP]

  30. Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems. [Citation Graph (, )][DBLP]

  31. A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. [Citation Graph (, )][DBLP]

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