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Joseph R. Cavallaro: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sridhar Rajagopal, Joseph R. Cavallaro
    On-line Arithmetic for Detection in Digital Communication Receivers. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:257-265 [Conf]
  2. Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro
    Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:260-270 [Conf]
  3. B. Haller, J. Goetze, Joseph R. Cavallaro
    Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:162-0 [Conf]
  4. Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro
    Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:360-367 [Conf]
  5. Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang
    Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:173-184 [Conf]
  6. Martin L. Leuschen, Joseph R. Cavallaro, Ian D. Walker
    Robotic Fault Detection using Nonlinear Analytical Redundancy. [Citation Graph (0, 0)][DBLP]
    ICRA, 2002, pp:456-463 [Conf]
  7. M. L. Visinsky, Ian D. Walker, Joseph R. Cavallaro
    Layered Dynamic Fault Detection and Tolerance for Robots. [Citation Graph (0, 0)][DBLP]
    ICRA (2), 1993, pp:180-187 [Conf]
  8. M. L. Visinsky, Ian D. Walker, Joseph R. Cavallaro
    New Dynamic Model-Based Fault Detection Thresholds for Robot Manipulators. [Citation Graph (0, 0)][DBLP]
    ICRA, 1994, pp:1388-1395 [Conf]
  9. Ian D. Walker, Joseph R. Cavallaro
    Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots. [Citation Graph (0, 0)][DBLP]
    ICRA (1), 1993, pp:870-877 [Conf]
  10. Ian D. Walker, Joseph R. Cavallaro, Martin L. Leuschen
    Keeping the Analog Genie in the Bottle: A Case for Digital Robots. [Citation Graph (0, 0)][DBLP]
    ICRA, 1999, pp:1063-1070 [Conf]
  11. Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro
    Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:77-80 [Conf]
  12. Sridhar Rajagopal, Joseph R. Cavallaro
    A bit-streaming, pipelined multiuser detector for wireless communication receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:128-131 [Conf]
  13. Yuanbin Guo, Joseph R. Cavallaro
    Post-compensation of RF non-linearity in mobile OFDM systems by estimation of memory-less polynomial. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:217-220 [Conf]
  14. Yuanbin Guo, Joseph R. Cavallaro
    A novel adaptive pre-distorter using LS estimation of SSPA non-linearity in mobile OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:453-456 [Conf]
  15. Frank Livingston, Vikram Chandrasekhar, M. Vaya, Joseph R. Cavallaro
    Handset detector architectures for DS-CDMA wireless systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:265-268 [Conf]
  16. Marjan Karkooti, Joseph R. Cavallaro
    Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2004, pp:579-585 [Conf]
  17. Manik Gadhiok, Ricky Hardy, Patrick Murphy, J. Patrick Frantz, Hyeokho Choi, Joseph R. Cavallaro
    An FPGA-Based Daughtercard for TI's C6000 family of DSKs. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:85-86 [Conf]
  18. Patrick Murphy, J. Patrick Frantz, Erik Welsh, Ricky Hardy, Tinoosh Mohsenin, Joseph R. Cavallaro
    VALID: Custom ASIC Verification and FPGA Education Platform. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:64-65 [Conf]
  19. Arati S. Deo, Joseph R. Cavallaro, Ian D. Walker
    New Real-Time Robot Motion Algorithms Using Parallel VLSI Architectures. [Citation Graph (0, 0)][DBLP]
    PPSC, 1991, pp:369-375 [Conf]
  20. Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cavallaro
    Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:179-185 [Conf]
  21. Joseph R. Cavallaro, Franklin T. Luk
    CORDIC Arithmetic for an SVD Processor. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1988, v:5, n:3, pp:271-290 [Journal]
  22. Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner
    Design Space Exploration for Real-Time Embedded Stream Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:4, pp:54-66 [Journal]
  23. Panagiotis Demestichas, Guillaume Vivier, Joseph R. Cavallaro
    Special Issue on Reconfigurable Radio Technologies in Support of Ubiquitous Seamless Computing. [Citation Graph (0, 0)][DBLP]
    MONET, 2006, v:11, n:6, pp:775-777 [Journal]
  24. Nariankadu D. Hemkumar, Joseph R. Cavallaro
    Redundant and On-Line CORDIC for Unitary Transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:8, pp:941-954 [Journal]
  25. Kishore Kota, Joseph R. Cavallaro
    Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:7, pp:769-779 [Journal]
  26. Sridhar Rajagopal, Joseph R. Cavallaro
    Truncated Online Arithmetic with Applications to Communication Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:10, pp:1240-12529 [Journal]
  27. Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
    VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2104-2107 [Conf]
  28. Yuanbin Guo, Joseph R. Cavallaro
    A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:195-217 [Journal]

  29. Efficient complex matrix transformations with CORDIC. [Citation Graph (, )][DBLP]

  30. Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. [Citation Graph (, )][DBLP]

  31. Programming high performance signal processing systems in high level languages. [Citation Graph (, )][DBLP]

  32. High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm. [Citation Graph (, )][DBLP]

  33. Adaptive codebook for beamforming in limited feedback MIMO systems. [Citation Graph (, )][DBLP]

  34. Implementation Aspects of List Sphere Detector Algorithms. [Citation Graph (, )][DBLP]

  35. Novel Sort-Free Detector with Modified Real-Valued Decomposition (M-RVD) Ordering in MIMO Systems. [Citation Graph (, )][DBLP]

  36. QRD-QLD Searching Based Sphere Detection for Emerging MIMO Downlink OFDM Receivers. [Citation Graph (, )][DBLP]

  37. A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards. [Citation Graph (, )][DBLP]

  38. Cooperative Communications Using Scalable, Medium Block-length LDPC Codes. [Citation Graph (, )][DBLP]

  39. Comparison of Two Novel List Sphere Detector Algorithms for MIMO-OFDM Systems. [Citation Graph (, )][DBLP]

  40. Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area. [Citation Graph (, )][DBLP]

  41. Unified decoder architecture for LDPC/turbo codes. [Citation Graph (, )][DBLP]

  42. A GPU implementation of a real-time MIMO detector. [Citation Graph (, )][DBLP]

  43. Design of block-structured LDPC codes for iterative receivers with soft sphere detection. [Citation Graph (, )][DBLP]

  44. Architecture design and implementation of the increasing radius - List sphere detector algorithm. [Citation Graph (, )][DBLP]

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