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Miriam Leeser: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter Soderquist, Miriam Leeser
    An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:132-139 [Conf]
  2. Waleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai
    Architectural Design of a Three Dimensional FPGA. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:256-269 [Conf]
  3. Mark Aagaard, Miriam Leeser
    Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:69-81 [Conf]
  4. John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark Aagaard
    HML: A Hardware Description Language Based on Standard ML. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:327-334 [Conf]
  5. Shantanu Tarafdar, Miriam Leeser
    The DT-Model: High-Level Synthesis Using Data Transfers. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:114-117 [Conf]
  6. Laurie A. Smith King, Miriam Leeser, Heather Quinn
    Dynamo: A Runtime Partitioning System. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:145-154 [Conf]
  7. Joshua Noseworthy, Miriam Leeser
    Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:191-197 [Conf]
  8. Goran Doncev, Miriam Leeser, Shantanu Tarafdar
    High Level Synthesis for Designing Custom Computing Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:326-328 [Conf]
  9. Miriam Leeser, Shawn Miller, Haiqian Yu
    Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:147-155 [Conf]
  10. Haiqian Yu, Miriam Leeser
    Automatic Sliding Window Operation Optimization for FPGA-Based. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:76-88 [Conf]
  11. Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis
    Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:173-0 [Conf]
  12. Xiaojun Wang, Sherman Braganza, Miriam Leeser
    Advanced Components in the Variable Precision Floating-Point Library. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:249-258 [Conf]
  13. Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel
    Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:264- [Conf]
  14. Srdjan Coric, Miriam Leeser, Eric Miller, Marc Trepanier
    Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:217-226 [Conf]
  15. Wang Chen, Panos Kosmas, Miriam Leeser, Carey Rappaport
    An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:213-222 [Conf]
  16. Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski
    Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:103-110 [Conf]
  17. Ali M. Shankiti, Miriam Leeser
    Implementing a RAKE receiver for wireless communications on an FPGA-based computer system. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:145-151 [Conf]
  18. Joshua Noseworthy, Miriam Leeser
    Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:233- [Conf]
  19. Pavle Belanovic, Miriam Leeser
    A Library of Parameterized Floating-Point Modules and Their Use. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:657-666 [Conf]
  20. Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Paul M. Zavracky
    Rothko: A three dimensional FPGA architecture, its fabrication, and design tools. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:21-30 [Conf]
  21. Mark H. Linderman, Miriam Leeser
    Simulation of digital circuits in the presence of uncertainty. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:248-251 [Conf]
  22. Shantanu Tarafdar, Miriam Leeser, Zixin Yin
    Integrating floorplanning in data-transfer based high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:412-417 [Conf]
  23. Mark Aagaard, Miriam Leeser
    A Formally Verified System for Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:346-350 [Conf]
  24. Mark Aagaard, Miriam Leeser
    A Framework for Specifying and Designing Pipelines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:548-551 [Conf]
  25. Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos
    Run-Time Execution of Reconfigurable Hardware in a Java Environment. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:380-387 [Conf]
  26. Miriam Leeser, John W. O'Leary
    Verification of a subtractive radix-2 square root algorithm and implementation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:526-531 [Conf]
  27. Peter Soderquist, Miriam Leeser
    Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:417-422 [Conf]
  28. Juan Carlos Rojas, Miriam Leeser
    Programming portable optimized multimedia applications. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2003, pp:291-294 [Conf]
  29. Peter Soderquist, Miriam Leeser
    Optimizing the Data Cache Performance of a Software MPEG-2 Video Decoder. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 1997, pp:291-301 [Conf]
  30. Geoffrey M. Brown, Miriam Leeser
    From Programs to Transistors: Verifying Hardware Synthesis Tools. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:129-151 [Conf]
  31. Goran Doncev, Miriam Leeser, Shantanu Tarafdar
    Truly Rapid Prototyping Requires High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:101-0 [Conf]
  32. Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel
    Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:128-134 [Conf]
  33. Ben Cordes, Miriam Leeser, Eric Miller, Richard W. Linderman
    Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:149- [Conf]
  34. Mark Aagaard, Miriam Leeser
    Reasoning About Pipelines with Structural Hazards. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:13-32 [Conf]
  35. John W. O'Leary, Miriam Leeser, Jason Hickey, Mark Aagaard
    Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:52-71 [Conf]
  36. Mark Aagaard, Miriam Leeser
    A Methodology for Reusable Hardware Proofs. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:177-196 [Conf]
  37. Mark Aagaard, Miriam Leeser, Phillip J. Windley
    Toward a Super Duper Hardware Tactic. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:399-412 [Conf]
  38. Peter Soderquist, Miriam Leeser
    Area and Performance Tradeoffs in Floating-Point Divide and Square-Root Implementations. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:3, pp:518-564 [Journal]
  39. Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, Weidong Xu, Paul M. Zavracky
    Rothko: A Three-Dimensional FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:16-23 [Journal]
  40. Mark Aagaard, Miriam Leeser
    A Methodology for Efficient Hardware Verification. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:5, n:1/2, pp:95-117 [Journal]
  41. Andrés Takach, Wayne Wolf, Miriam Leeser
    An Automaton Model for Scheduling Constraints in Synchronous Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:1, pp:1-12 [Journal]
  42. Mark Aagaard, Miriam Leeser
    PBS: proven Boolean simplification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:459-470 [Journal]
  43. Miriam Leeser
    Reasoning about the function and timing of integrated circuits with interval temporal logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1233-1246 [Journal]
  44. Shantanu Tarafdar, Miriam Leeser
    A data-centric approach to high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1251-1267 [Journal]
  45. Peter Soderquist, Miriam Leeser, Juan Carlos Rojas
    Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2006, v:8, n:1, pp:81-89 [Journal]
  46. Mark Aagaard, Miriam Leeser
    Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1995, v:21, n:10, pp:822-833 [Journal]
  47. Yanbing Li, Miriam Leeser
    HML, a novel hardware description language and its translation to VHDL. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:1-8 [Journal]
  48. Silviu M. S. A. Chiricescu, Miriam Leeser, Mankuan Michael Vai
    Design and analysis of a dynamically reconfigurable three-dimensional FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:186-196 [Journal]

  49. The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  50. An efficient implementation of a phase unwrapping kernel on reconfigurable hardware. [Citation Graph (, )][DBLP]


  51. Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  52. Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA. [Citation Graph (, )][DBLP]


  53. The Effect of Parameterization on a Reconfigurable Implementation of PIV. [Citation Graph (, )][DBLP]


  54. K-means Clustering for Multispectral Images Using Floating-Point Divide. [Citation Graph (, )][DBLP]


  55. Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  56. An FPGA Implementation of Explicit-State Model Checking. [Citation Graph (, )][DBLP]


  57. An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  58. Efficient FPGA implementation of qr decomposition using a systolic array architecture. [Citation Graph (, )][DBLP]


  59. Vforce: An Extensible Framework for Reconfigurable Supercomputing. [Citation Graph (, )][DBLP]


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