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Mircea R. Stan :
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Mircea R. Stan Synchronous Up/Down Counter with Clock Period Independent of Counter Size. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 1997, pp:274-281 [Conf ] Zhijian Lu , Jason Hein , Marty Humphrey , Mircea R. Stan , John Lach , Kevin Skadron Control-theoretic dynamic frequency and voltage scaling for multimedia workloads. [Citation Graph (0, 0)][DBLP ] CASES, 2002, pp:156-163 [Conf ] Lei He , Weiping Liao , Mircea R. Stan System level leakage reduction considering the interdependence of temperature and leakage. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:12-17 [Conf ] Wei Huang , Mircea R. Stan , Kevin Skadron , Karthik Sankaranarayanan , Shougata Ghosh , Sivakumar Velusamy Compact thermal modeling for temperature-aware design. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:878-883 [Conf ] Yan Zhang , Zhijian Lu , John Lach , Kevin Skadron , Mircea R. Stan Optimal procrastinating voltage scheduling for hard real-time systems. [Citation Graph (0, 0)][DBLP ] DAC, 2005, pp:905-908 [Conf ] Yingmin Li , Dharmesh Parikh , Yan Zhang , Karthik Sankaranarayanan , Mircea R. Stan , Kevin Skadron State-Preserving vs. Non-State-Preserving Leakage Control in Caches. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:22-29 [Conf ] Zhijian Lu , Yan Zhang , Mircea R. Stan , John Lach , Kevin Skadron Procrastinating voltage scheduling with discrete frequency sets. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:456-461 [Conf ] Mircea R. Stan , Avishek Panigrahi The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:1106- [Conf ] Matthew M. Ziegler , Mircea R. Stan A Unified Design Space for Regular Parallel Prefix Adders. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:1386-1387 [Conf ] Garrett S. Rose , Mircea R. Stan A programmable majority logic array using molecular scale electronics. [Citation Graph (0, 0)][DBLP ] FPGA, 2006, pp:225- [Conf ] Garrett S. Rose , Adam C. Cabe , Nadine Gergel-Hackett , Nabanita Majumdar , Mircea R. Stan , John C. Bean , Lloyd R. Harriott , Yuxing Yao , James M. Tour Design approaches for hybrid CMOS/molecular memory based on experimental device data. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:2-7 [Conf ] Mircea R. Stan , Wayne P. Burleson Coding a terminated bus for low power. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1995, pp:70-73 [Conf ] Yan Zhang , Mircea R. Stan Temperature-aware circuit design using adaptive body biasing. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2007, pp:84-89 [Conf ] Matthew M. Ziegler , Gary S. Ditlow , Stephen V. Kosonocky , Zhenyu (Jerry) Qi , Mircea R. Stan Structured and tuned array generation (STAG) for high-performance random logic. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2007, pp:257-262 [Conf ] Dharmesh Parikh , Kevin Skadron , Yan Zhang , Marco Barcella , Mircea R. Stan Power Issues Related to Branch Prediction. [Citation Graph (0, 0)][DBLP ] HPCA, 2002, pp:233-0 [Conf ] Kevin Skadron , Tarek F. Abdelzaher , Mircea R. Stan Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management. [Citation Graph (0, 0)][DBLP ] HPCA, 2002, pp:17-28 [Conf ] Zhijian Lu , Wei Huang , John Lach , Mircea R. Stan , Kevin Skadron Interconnect lifetime prediction under dynamic stress for reliability-aware design. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:327-334 [Conf ] Matthew M. Ziegler , Mircea R. Stan A Case for CMOS/nano co-design. [Citation Graph (0, 0)][DBLP ] ICCAD, 2002, pp:348-352 [Conf ] Zhijian Lu , John Lach , Mircea R. Stan , Kevin Skadron Reducing Multimedia Decode Power using Feedback Control. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:489-0 [Conf ] Sivakumar Velusamy , Wei Huang , John Lach , Mircea R. Stan , Kevin Skadron Monitoring Temperature in FPGA based SoCs. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:634-640 [Conf ] Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan Temperature-Aware Microarchitecture. [Citation Graph (0, 0)][DBLP ] ISCA, 2003, pp:2-13 [Conf ] Mircea R. Stan , Marco Barcella MTCMOS with outer feedback (MTOF) flip-flops. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:429-432 [Conf ] Yan Zhang , Travis Blalock , Mircea R. Stan A three-level toggle-avoid bus signaling scheme. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2005, pp:1843-1846 [Conf ] Matthew M. Ziegler , Mircea R. Stan The CMOS/nano interface from a circuits perspective. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2003, pp:904-907 [Conf ] Joshua L. Garrett , Mircea R. Stan Active threshold compensation circuit for improved performance in cooled CMOS systems. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2001, pp:410-413 [Conf ] David Garrett , Mircea R. Stan A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2001, pp:61-64 [Conf ] Mircea R. Stan Systolic counters with unique zero state. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2004, pp:909-912 [Conf ] Fatih Hamzaoglu , Mircea R. Stan Circuit-level techniques to control gate leakage for sub-100nm CMOS. [Citation Graph (0, 0)][DBLP ] ISLPED, 2002, pp:60-63 [Conf ] David Garrett , Mircea R. Stan Power reduction techniques for a spread spectrum based correlator. [Citation Graph (0, 0)][DBLP ] ISLPED, 1997, pp:225-230 [Conf ] David Garrett , Mircea R. Stan Low power architecture of the soft-output Viterbi algorithm. [Citation Graph (0, 0)][DBLP ] ISLPED, 1998, pp:262-267 [Conf ] David Garrett , Mircea R. Stan , Alvar Dean Challenges in clockgating for a low power ASIC methodology. [Citation Graph (0, 0)][DBLP ] ISLPED, 1999, pp:176-181 [Conf ] Wei Huang , Eric Humenay , Kevin Skadron , Mircea R. Stan The need for a full-chip and package thermal model for thermally optimized IC designs. [Citation Graph (0, 0)][DBLP ] ISLPED, 2005, pp:245-250 [Conf ] Mircea R. Stan Low threshold CMOS circuits with low standby current. [Citation Graph (0, 0)][DBLP ] ISLPED, 1998, pp:97-99 [Conf ] Mircea R. Stan , Wayne P. Burleson Two dimensional codes for low power. [Citation Graph (0, 0)][DBLP ] ISLPED, 1996, pp:335-340 [Conf ] Yan Zhang , John Lach , Kevin Skadron , Mircea R. Stan Odd/even bus invert with two-phase transfer for buses with coupling. [Citation Graph (0, 0)][DBLP ] ISLPED, 2002, pp:80-83 [Conf ] Zhenyu (Jerry) Qi , Matthew M. Ziegler , Stephen V. Kosonocky , Jan M. Rabaey , Mircea R. Stan Multi-Dimensional Circuit and Micro-Architecture Level Optimization. [Citation Graph (0, 0)][DBLP ] ISQED, 2007, pp:275-280 [Conf ] Mircea R. Stan , Yan Zhang Perfect 3-Limited-Weight Code for Low Power I/O. [Citation Graph (0, 0)][DBLP ] PATMOS, 2004, pp:79-89 [Conf ] Mircea R. Stan , Fatih Hamzaoglu , David Garrett Non-Manhattan maze routing. [Citation Graph (0, 0)][DBLP ] SBCCI, 2004, pp:260-265 [Conf ] Mircea R. Stan Optimal Voltages and Sizing for Low Power. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:428-433 [Conf ] Mircea R. Stan , Garrett S. Rose , Matthew M. Ziegler Hybrid CMOS/Molecular Electronic Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:703-708 [Conf ] Mircea R. Stan , Kevin Skadron Guest Editors' Introduction: Power-Aware Computing. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2003, v:36, n:12, pp:35-38 [Journal ] Mircea R. Stan CMOS Circuits with Subvolt Supply Voltages. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2002, v:19, n:2, pp:34-43 [Journal ] Zhijian Lu , John Lach , Mircea R. Stan , Kevin Skadron Alloyed Branch History: Combining Global and Local Branch History for Robust Performance. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2003, v:31, n:2, pp:137-177 [Journal ] Zhijian Lu , John Lach , Mircea R. Stan , Kevin Skadron Improved Thermal Management with Reliability Banking. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2005, v:25, n:6, pp:40-49 [Journal ] Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan Temperature-Aware Computer Systems: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2003, v:23, n:6, pp:52-61 [Journal ] Kevin Skadron , Mircea R. Stan , Karthik Sankaranarayanan , Wei Huang , Sivakumar Velusamy , David Tarjan Temperature-aware microarchitecture: Modeling and implementation. [Citation Graph (0, 0)][DBLP ] TACO, 2004, v:1, n:1, pp:94-125 [Journal ] Dharmesh Parikh , Kevin Skadron , Yan Zhang , Mircea R. Stan Power-Aware Branch Prediction: Characterization and Design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2004, v:53, n:2, pp:168-186 [Journal ] Mircea R. Stan , Alexandre F. Tenca , Milos D. Ercegovac Long and Fast Up/Down Counters. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:7, pp:722-735 [Journal ] Wei Huang , Shougata Ghosh , Sivakumar Velusamy , Karthik Sankaranarayanan , Kevin Skadron , Mircea R. Stan HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:501-513 [Journal ] Garrett S. Rose , Matthew M. Ziegler , Mircea R. Stan Large-signal two-terminal device model for nanoelectronic circuit analysis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1201-1208 [Journal ] Yan Zhang , Sudhanva Gurumurthi , Mircea R. Stan SODA: Sensitivity Based Optimization of Disk Architecture. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:865-870 [Conf ] Garrett S. Rose , Yuxing Yao , James M. Tour , Adam C. Cabe , Nadine Gergel-Hackett , Nabanita Majumdar , John C. Bean , Lloyd R. Harriott , Mircea R. Stan Designing CMOS/molecular memories while considering device parameter variations. [Citation Graph (0, 0)][DBLP ] JETC, 2007, v:3, n:1, pp:- [Journal ] Zhijian Lu , Wei Huang , Mircea R. Stan , Kevin Skadron , John Lach Interconnect Lifetime Prediction for Reliability-Aware Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:159-172 [Journal ] Mircea R. Stan , Wayne P. Burleson Bus-invert coding for low-power I/O. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:49-58 [Journal ] Mircea R. Stan , Wayne P. Burleson Low-power encodings for global communication in CMOS VLSI. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:444-455 [Journal ] Mircea R. Stan Low-power CMOS with subvolt supply voltages. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:394-400 [Journal ] Mircea R. Stan , Kevin Skadron , Marco Barcella , Wei Huang , Karthik Sankaranarayanan , Sivakumar Velusamy HotSpot: a dynamic compact thermal model at the processor-architecture level. [Citation Graph (0, 0)][DBLP ] Microelectronics Journal, 2003, v:34, n:12, pp:1153-1165 [Journal ] Many-core design from a thermal perspective. [Citation Graph (, )][DBLP ] SRAM-based NBTI/PBTI sensor system design. [Citation Graph (, )][DBLP ] Stacking SRAM banks for ultra low power standby mode operation. [Citation Graph (, )][DBLP ] FlashPower: A detailed power model for NAND flash memory. [Citation Graph (, )][DBLP ] NBTI resilient circuits using adaptive body biasing. [Citation Graph (, )][DBLP ] Intra-disk Parallelism: An Idea Whose Time Has Come. [Citation Graph (, )][DBLP ] Differentiating the roles of IR measurement and simulation for power and temperature-aware design. [Citation Graph (, )][DBLP ] Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. [Citation Graph (, )][DBLP ] Sensitivity Based Power Management of Enterprise Storage Systems. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.305secs