The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Haridimos T. Vergos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:211-217 [Conf]
  2. Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    A Family of Parallel-Pre.x Modulo 2n - 1 Adders. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:326-336 [Conf]
  3. G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos
    Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:47-52 [Conf]
  4. Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
    Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:112-116 [Conf]
  5. Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
    Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:121-129 [Conf]
  6. Haridimos T. Vergos, Costas Efstathiou
    Diminished-1 Modulo 2n + 1 Squarer Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:380-386 [Conf]
  7. Haridimos T. Vergos, Costas Efstathiou
    Novel Modulo 2n + 1 Multipliers. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:168-175 [Conf]
  8. Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos
    Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:267-282 [Conf]
  9. Dimitris Nikolos, Haridimos T. Vergos
    On the Yield of VLSI Processors with on-chip CPU Cache. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:214-230 [Conf]
  10. Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis
    On Path Delay Fault Testing of Multiplexer - Based Shifters. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:20-23 [Conf]
  11. C. Ninos, Haridimos T. Vergos, Dimitris Nikolos
    Design and Analysis of On-Chip CPU Pipelined Caches. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:161-172 [Conf]
  12. D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
    An Efficient BIST scheme for High-Speed Adders. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:89-93 [Conf]
  13. Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:225-228 [Conf]
  14. D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
    Efficient BIST schemes for RNS datapaths. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:573-576 [Conf]
  15. Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos
    Low Power BIST for Wallace Tree-Based Fast Multipliers. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:433-438 [Conf]
  16. Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
    On Accumulator-Based Bit-Serial Test Response Compaction Schemes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:350-0 [Conf]
  17. Nikolaos Kostaras, Haridimos T. Vergos
    KoVer: A Sophisticated Residue Arithmetic Core Generator. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:261-263 [Conf]
  18. Haridimos T. Vergos, Costas Efstathiou
    On the Design of Efficient Modular Adders. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:5, pp:965-972 [Journal]
  19. Dimitris Bakalis, K. Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
    A core generator for arithmetic cores and testing structures with a network interface. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:1, pp:1-12 [Journal]
  20. Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou
    On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:4-5, pp:125-135 [Journal]
  21. Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
    Efficient Diminished-1 Modulo 2^n+1 Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:4, pp:491-496 [Journal]
  22. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Modulo 2n±1 Adder Design Using Select-Prefix Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1399-1406 [Journal]
  23. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Modified Booth Modulo 2n-1 Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:370-374 [Journal]
  24. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Fast Parallel-Prefix Modulo 2^n+1 Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1211-1216 [Journal]
  25. Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
    High-Speed Parallel-Prefix Modulo 2n-1 Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:673-680 [Journal]
  26. Dimitris Nikolos, Haridimos T. Vergos
    On the Yield of VLSI Processors with On-Chip CPU Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:10, pp:1138-1144 [Journal]
  27. Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
    Diminished-One Modulo 2n+1 Adder Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:12, pp:1389-1399 [Journal]
  28. Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
    Deterministic BIST for RNS Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:7, pp:896-906 [Journal]

  29. An Efficient BIST Scheme for Non-Restoring Array Dividers. [Citation Graph (, )][DBLP]


  30. On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002