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Title:
Author:
Dimitris Nikolos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:211-217 [Conf]
  2. Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
    An Energy-Delay Efficient Subword Permutation Unit. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:245-252 [Conf]
  3. Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    A Family of Parallel-Pre.x Modulo 2n - 1 Adders. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:326-336 [Conf]
  4. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
    A ROMless LFSR Reseeding Scheme for Scan-based BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:206-0 [Conf]
  5. G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos
    Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:47-52 [Conf]
  6. Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis
    An efficient comparative concurrent Built-In Self-Test technique. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:309-315 [Conf]
  7. Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis
    Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. [Citation Graph (0, 0)][DBLP]
    Aegean Workshop on Computing, 1986, pp:144-155 [Conf]
  8. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
    Efficient test-data compression for IP cores using multilevel Huffman coding. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1033-1038 [Conf]
  9. Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
    Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:112-116 [Conf]
  10. Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos
    A Versatile Built-In Self-Test Scheme for Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:756- [Conf]
  11. Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas
    C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:155-163 [Conf]
  12. Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
    Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:121-129 [Conf]
  13. Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
    Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:128-136 [Conf]
  14. Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos
    Test Set Embedding Based on Phase Shifters. [Citation Graph (0, 0)][DBLP]
    EDCC, 2002, pp:90-101 [Conf]
  15. Maciej Bellos, Dimitris Nikolos
    Deterministic Test Vector Compression / Decompression Using an Embedded Processor. [Citation Graph (0, 0)][DBLP]
    EDCC, 2005, pp:318-331 [Conf]
  16. Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos
    Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:267-282 [Conf]
  17. Dimitris Nikolos, Haridimos T. Vergos
    On the Yield of VLSI Processors with on-chip CPU Cache. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:214-230 [Conf]
  18. C. Laoudias, Dimitris Nikolos
    A new test pattern generator for high defect coverage in a BIST environment. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:417-420 [Conf]
  19. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
    A highly regular multi-phase reseeding technique for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:295-298 [Conf]
  20. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
    A novel reseeding technique for accumulator-based test pattern generation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:7-12 [Conf]
  21. Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis
    On Path Delay Fault Testing of Multiplexer - Based Shifters. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:20-23 [Conf]
  22. Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou
    Systematic t-error correcting all unidirectional error detecting codes. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1984, pp:177-188 [Conf]
  23. C. Ninos, Haridimos T. Vergos, Dimitris Nikolos
    Design and Analysis of On-Chip CPU Pipelined Caches. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:161-172 [Conf]
  24. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
    A New Reseeding Technique for LFSR-Based Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:80-86 [Conf]
  25. P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos
    Accumulator based Test-per-Scan BIST. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:193-198 [Conf]
  26. Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis
    Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:152-157 [Conf]
  27. D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
    An Efficient BIST scheme for High-Speed Adders. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:89-93 [Conf]
  28. Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis
    A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:56-60 [Conf]
  29. Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos
    A Compact Built-In Current Sensor for IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:95-99 [Conf]
  30. Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou
    Concurrent Detection of Soft Errors Based on Current Monitoring. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:106-110 [Conf]
  31. Dimitris Nikolos, Dimitrios Kagaris, S. Gidaros
    Diophantine-Equation Based Arithmetic Test Set Embedding. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:193-194 [Conf]
  32. Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos
    Virtual-scan: a novel approach for software-based self-testing of microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:237-240 [Conf]
  33. Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:225-228 [Conf]
  34. D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
    Efficient BIST schemes for RNS datapaths. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:573-576 [Conf]
  35. Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos
    Low Power BIST for Wallace Tree-Based Fast Multipliers. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:433-438 [Conf]
  36. Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
    On Accumulator-Based Bit-Serial Test Response Compaction Schemes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:350-0 [Conf]
  37. Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
    Low Power Testing by Test Vector Ordering with Vector Repetition. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:205-210 [Conf]
  38. Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
    On Testability of Multiple Precharged Domino Logic. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:299-304 [Conf]
  39. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
    An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:261-266 [Conf]
  40. Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos
    Reseeding-Based Test Set Embedding with Reduced Test Sequences. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:226-231 [Conf]
  41. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
    Efficient Multiphase Test Set Embedding for Scan-based Testing. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:433-438 [Conf]
  42. Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
    Extending the Viability of IDDQ Testing in the Deep Submicron Era. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:100-105 [Conf]
  43. Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos
    Scan Cell Ordering for Low Power BIST. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:281-284 [Conf]
  44. Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos
    Low Power Test Set Embedding Based on Phase Shifters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:155-160 [Conf]
  45. Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
    An Efficient Test Vector Ordering Method for Low Power Testing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:285-288 [Conf]
  46. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
    Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:804-811 [Conf]
  47. Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis
    R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:918-925 [Conf]
  48. Giorgos Dimitrakopoulos, Dimitris Nikolos
    Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:308-317 [Conf]
  49. Giorgos Dimitrakopoulos, P. Kolovos, P. Kalogerakis, Dimitris Nikolos
    Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:248-257 [Conf]
  50. Dimitris Bakalis, K. Adaos, George Alexiou, Dimitris Nikolos, D. Lymperopoulos
    EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:182-187 [Conf]
  51. A. Vasilliou, K. Gounaris, K. Adaos, D. Mitsainas, George Alexiou, Dimitris Nikolos
    Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:21-0 [Conf]
  52. Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris
    DV-TSE: Difference Vector Based Test Set Embedding. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:343-0 [Conf]
  53. Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis
    Testing combinational iterative logic arrays for realistic faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:35-41 [Conf]
  54. Xrysovalantis Kavousianos, Dimitris Nikolos
    Self-exercising self testing k-order comparators. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:216-221 [Conf]
  55. Xrysovalantis Kavousianos, Dimitris Nikolos
    Novel Single and Double Output TSC Berger Code Checkers. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:348-353 [Conf]
  56. Xrysovalantis Kavousianos, Dimitris Nikolos
    Modular TSC Checkers for Bose-Lin and Bose Codes. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:354-360 [Conf]
  57. Xrysovalantis Kavousianos, Dimitris Nikolos, G. Foukarakis, T. Gnardellis
    New efficient totally self-checking Berger code checkers. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:28, n:1, pp:101-118 [Journal]
  58. Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis
    Testing CMOS combinational iterative logic arrays for realistic faults. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:3, pp:209-228 [Journal]
  59. Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
    A new technique for IDDQ testing in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:31, n:2, pp:183-194 [Journal]
  60. Dimitris Bakalis, K. Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
    A core generator for arithmetic cores and testing structures with a network interface. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:1, pp:1-12 [Journal]
  61. Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou
    On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:4-5, pp:125-135 [Journal]
  62. Vassilios V. Dimakopoulos, G. Sourtziotis, Antonis M. Paschalis, Dimitris Nikolos
    On TSC Checkers for m-out-n Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:8, pp:1055-1059 [Journal]
  63. Giorgos Dimitrakopoulos, Dimitris Nikolos
    High-Speed Parallel-Prefix VLSI Ling Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:2, pp:225-231 [Journal]
  64. Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
    Efficient Diminished-1 Modulo 2^n+1 Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:4, pp:491-496 [Journal]
  65. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Modulo 2n±1 Adder Design Using Select-Prefix Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1399-1406 [Journal]
  66. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Modified Booth Modulo 2n-1 Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:370-374 [Journal]
  67. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Fast Parallel-Prefix Modulo 2^n+1 Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1211-1216 [Journal]
  68. Th. Haniotakis, Antonis M. Paschalis, Dimitris Nikolos
    Efficient Totally Self-Checking Checkers for a Class of Borden Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:11, pp:1318-1322 [Journal]
  69. Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
    High-Speed Parallel-Prefix Modulo 2n-1 Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:673-680 [Journal]
  70. Dimitris Nikolos
    Theory and Design of t-Error Correcting/d-Error Detecting (d>t) and All Unidirectional Error Detecting Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:2, pp:132-142 [Journal]
  71. Dimitris Nikolos
    Optimal Self-Testing Embedded Parity Checkers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:3, pp:313-321 [Journal]
  72. Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou
    Systematic t-Error Correcting/All Unidirectional Error Detecting Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:5, pp:394-402 [Journal]
  73. Dimitris Nikolos, Alexandros Krokos
    Theory and Design of t-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting Codes with d > k > t. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:4, pp:411-419 [Journal]
  74. Dimitris Nikolos, Antonis M. Paschalis, George Philokyprou
    Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:7, pp:807-814 [Journal]
  75. Dimitris Nikolos, Haridimos T. Vergos
    On the Yield of VLSI Processors with On-Chip CPU Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:10, pp:1138-1144 [Journal]
  76. Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis
    Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:3, pp:301-309 [Journal]
  77. Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
    Diminished-One Modulo 2n+1 Adder Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:12, pp:1389-1399 [Journal]
  78. Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
    Deterministic BIST for RNS Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:7, pp:896-906 [Journal]
  79. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
    A new built-in TPG method for circuits with random patternresistant faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:859-866 [Journal]
  80. Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos
    On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2578-2586 [Journal]
  81. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
    Multiphase BIST: a new reseeding technique for high test-data compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1429-1446 [Journal]
  82. Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
    Fast bit permutation unit for media enhanced microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  83. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
    Optimal Selective Huffman Coding for Test-Data Compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:8, pp:1146-1152 [Journal]
  84. Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
    Testable Designs of Multiple Precharged Domino Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:461-465 [Journal]
  85. Giorgos Dimitrakopoulos, Christos Mavrokefalidis, K. Galanopoulos, Dimitris Nikolos
    Sorter Based Permutation Units for Media-Enhanced Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:711-715 [Journal]

  86. LFSR-based test-data compression with self-stoppable seeds. [Citation Graph (, )][DBLP]


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