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Costas Efstathiou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:211-217 [Conf]
  2. Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    A Family of Parallel-Pre.x Modulo 2n - 1 Adders. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:326-336 [Conf]
  3. Haridimos T. Vergos, Costas Efstathiou
    Diminished-1 Modulo 2n + 1 Squarer Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:380-386 [Conf]
  4. Haridimos T. Vergos, Costas Efstathiou
    Novel Modulo 2n + 1 Multipliers. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:168-175 [Conf]
  5. Costas Efstathiou, Constantine Halatsis
    Modular design of totally self-checking checkers for 1-out-of-n codes. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1984, pp:164-176 [Conf]
  6. D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
    An Efficient BIST scheme for High-Speed Adders. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:89-93 [Conf]
  7. Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou
    Concurrent Detection of Soft Errors Based on Current Monitoring. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:106-110 [Conf]
  8. Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
    A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:225-228 [Conf]
  9. D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
    Efficient BIST schemes for RNS datapaths. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:573-576 [Conf]
  10. Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
    On Testability of Multiple Precharged Domino Logic. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:299-304 [Conf]
  11. K. Katzourakis, George Kormentzas, Kimon P. Kontovasilis, Costas Efstathiou
    A Virtual Signalling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks. [Citation Graph (0, 0)][DBLP]
    MMNS, 2003, pp:259-271 [Conf]
  12. Haridimos T. Vergos, Costas Efstathiou
    On the Design of Efficient Modular Adders. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:5, pp:965-972 [Journal]
  13. Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
    Efficient Diminished-1 Modulo 2^n+1 Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:4, pp:491-496 [Journal]
  14. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Modulo 2n±1 Adder Design Using Select-Prefix Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1399-1406 [Journal]
  15. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Modified Booth Modulo 2n-1 Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:370-374 [Journal]
  16. Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
    Fast Parallel-Prefix Modulo 2^n+1 Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1211-1216 [Journal]
  17. Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
    High-Speed Parallel-Prefix Modulo 2n-1 Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:673-680 [Journal]
  18. Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis
    An Efficient TSC 1-out-of-3 Code Checker. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:407-411 [Journal]
  19. Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
    Diminished-One Modulo 2n+1 Adder Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:12, pp:1389-1399 [Journal]
  20. Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
    Deterministic BIST for RNS Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:7, pp:896-906 [Journal]
  21. Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
    Testable Designs of Multiple Precharged Domino Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:461-465 [Journal]

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