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Nestoras Tzartzanis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. William C. Athas, Nestoras Tzartzanis
    Energy recovery for low-power CMOS. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:415-429 [Conf]
  2. Nestoras Tzartzanis, William C. Athas
    Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:137-153 [Conf]
  3. Manolis Katevenis, Nestoras Tzartzanis
    Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1991, pp:15-27 [Conf]
  4. Nestoras Tzartzanis, William C. Athas
    Design and analysis of a low-power energy-recovery adder. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:66-69 [Conf]
  5. Nestoras Tzartzanis, William W. Walker
    A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:107-0 [Conf]
  6. William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson, Huimin Li, Xing Yu Jiang, Peiqing Wang, W.-C. Liu
    AC-1: a clock-powered microprocessor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:328-333 [Conf]
  7. Nestoras Tzartzanis, William C. Athas
    Energy recovery for the design of high-speed, low-power static RAMs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:55-60 [Conf]
  8. Nestoras Tzartzanis, William C. Athas
    Retractile clock-powered logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:18-23 [Conf]
  9. H. Ando, Nestoras Tzartzanis, William W. Walker
    A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:865-868 [Journal]
  10. William C. Athas, Lars J. Svensson, J. G. Koller, Nestoras Tzartzanis, E. Ying-Chin Chou
    Low-power digital systems based on adiabatic-switching principles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:398-407 [Journal]

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