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Steven M. Nowick: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Martin Benes, Andrew Wolfe, Steven M. Nowick
    A High-Speed Asynchronous Decompression Circuit for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:219-237 [Conf]
  2. Robert M. Fuhrer, Bill Lin, Steven M. Nowick
    Algorithms for the optimal state assignment of asynchronous state machines. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:59-75 [Conf]
  3. Yee William Li, George Patounakis, Anup Jose, Kenneth L. Shepard, Steven M. Nowick
    Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:216-226 [Conf]
  4. Martin Benes, Steven M. Nowick, Andrew Wolfe
    A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:43-0 [Conf]
  5. Tiberiu Chelcea, Steven M. Nowick
    Low-Latency Asynchronous FIFO's Using Token Rings. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:210-0 [Conf]
  6. Michael Theobald, Steven M. Nowick
    An Implicit Method for Hazard-Free Two-Level Logic Minimization. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:58-69 [Conf]
  7. José A. Tierno, Sergey Rylov, Alexander Rylyakov, Montek Singh, Steven M. Nowick
    An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:84-0 [Conf]
  8. Montek Singh, Steven M. Nowick
    High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:198-0 [Conf]
  9. Steven M. Nowick, Charles W. O'Donnell
    On the Existence of Hazard-Free Multi-Level Logic. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:109-120 [Conf]
  10. Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel
    Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:210-0 [Conf]
  11. Cheoljoo Jeong, Steven M. Nowick
    Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:128-137 [Conf]
  12. Melinda Y. Agyekum, Steven M. Nowick
    A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:129-142 [Conf]
  13. Amitava Mitra, William F. McLaughlin, Steven M. Nowick
    Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:186-195 [Conf]
  14. Peggy B. McGee, Steven M. Nowick, Edward G. Coffman Jr.
    Efficient performance analysis of asynchronous systems based on periodicity. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:225-230 [Conf]
  15. Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
    Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:104-109 [Conf]
  16. Tiberiu Chelcea, Steven M. Nowick
    Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:21-26 [Conf]
  17. Tiberiu Chelcea, Steven M. Nowick
    Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:405-410 [Conf]
  18. Cheoljoo Jeong, Steven M. Nowick
    Fast hazard detection in combinational circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:592-595 [Conf]
  19. Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick
    Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:77-82 [Conf]
  20. Peggy B. McGee, Steven M. Nowick
    A lattice-based framework for the classification and design of asynchronous pipelines. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:491-496 [Conf]
  21. Michael Theobald, Steven M. Nowick
    Transformations for the Synthesis and Optimization of Asynchronous Distributed Control. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:263-268 [Conf]
  22. Michael Theobald, Steven M. Nowick, Tao Wu
    Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:71-76 [Conf]
  23. Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug Edwards
    A Burst-Mode Oriented Back-End for the Balsa Synthesis System. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:330-337 [Conf]
  24. Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick
    High-Speed Non-Linear Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1000-1007 [Conf]
  25. Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh
    Estimation and bounding of energy consumption in burst-mode control circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:26-33 [Conf]
  26. Robert M. Fuhrer, Bill Lin, Steven M. Nowick
    Symbolic hazard-free minimization and encoding of asynchronous finite state machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:604-611 [Conf]
  27. Robert M. Fuhrer, Steven M. Nowick
    OPTIMIST: state minimization for optimal 2-level logic implementation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:308-315 [Conf]
  28. Robert M. Fuhrer, Steven M. Nowick
    OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:7-13 [Conf]
  29. Steven M. Nowick, David L. Dill
    Automatic Synthesis of Locally-Clocked Asynchronous State Machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:318-321 [Conf]
  30. Steven M. Nowick, David L. Dill
    Exact two-level minimization of hazard-free logic with multiple-input changes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:626-630 [Conf]
  31. Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
    Practical Advances in Asynchronous Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:662-668 [Conf]
  32. Steven M. Nowick, Bill Coates
    UCLOCK: Automated Design of High-Peformance Unclocked State Machines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:434-441 [Conf]
  33. Steven M. Nowick, David L. Dill
    Synthesis of Asynchronous State Machines Using A Local Clock. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:192-197 [Conf]
  34. Steven M. Nowick, Kenneth Y. Yun, David L. Dill
    Practical Asynchronous Controller Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:341-345 [Conf]
  35. Montek Singh, Steven M. Nowick
    MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:9-17 [Conf]
  36. Kenneth Y. Yun, David L. Dill, Steven M. Nowick
    Synthesis of 3D Asynchronous State Machines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:346-350 [Conf]
  37. Steven M. Nowick, Michael Theobald
    Synthesis of low-power asynchronous circuits in a specified environment. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:92-95 [Conf]
  38. Luis A. Plana, Steven M. Nowick
    Concurrency-oriented optimization for low-power asynchronous systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:151-156 [Conf]
  39. Montek Singh, Steven M. Nowick
    Synthesis-for-Initializability of Asynchronous Sequential Machines. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:232-241 [Conf]
  40. Tiberiu Chelcea, Steven M. Nowick
    Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:355-360 [Conf]
  41. Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:171-176 [Conf]
  42. Montek Singh, Steven M. Nowick
    Synthesis for Logical Initializability of Synchronous Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:76-81 [Conf]
  43. David L. Dill, Steven M. Nowick, Robert F. Sproull
    Specification and Automatic Verification of Self-Timed Queues. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1992, v:1, n:1, pp:29-60 [Journal]
  44. Ganesh Gopalakrishnan, Erik Brunvand, Nick Michell, Steven M. Nowick
    A correctness criterion for asynchronous circuit validation and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:11, pp:1309-1318 [Journal]
  45. Soha Hassoun, Steven M. Nowick, Leon Stok
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:662-664 [Journal]
  46. Steven M. Nowick, David L. Dill
    Exact two-level minimization of hazard-free logic with multiple-input changes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:986-997 [Journal]
  47. Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1514-1521 [Journal]
  48. Michael Theobald, Steven M. Nowick
    Fast heuristic and exact algorithms for two-level hazard-free logic minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1130-1147 [Journal]
  49. Tiberiu Chelcea, Steven M. Nowick
    Robust interfaces for mixed-timing systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:857-873 [Journal]
  50. Montek Singh, Steven M. Nowick
    The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1256-1269 [Journal]
  51. Montek Singh, Steven M. Nowick
    The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1270-1283 [Journal]
  52. Montek Singh, Steven M. Nowick
    MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:684-698 [Journal]
  53. Luis A. Plana, Steven M. Nowick
    Architectural optimization for low-power nonpipelined asynchronous systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:56-65 [Journal]
  54. Montek Singh, Steven M. Nowick
    Synthesis for logical initializability of synchronous finite-state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:542-557 [Journal]

  55. Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation. [Citation Graph (, )][DBLP]


  56. An error-correcting unordered code and hardware support for robust asynchronous global communication. [Citation Graph (, )][DBLP]


  57. An efficient algorithm for time separation of events in concurrent systems. [Citation Graph (, )][DBLP]


  58. A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors. [Citation Graph (, )][DBLP]


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