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Marios C. Papaefthymiou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kumar N. Lalgudi, Marios C. Papaefthymiou
    Efficient retiming under a general delay model. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:368-382 [Conf]
  2. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
    Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:42-58 [Conf]
  3. Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou
    Symbolic debugging of globally optimized behavioral specifications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:397-400 [Conf]
  4. Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
    Fast, efficient, recovering, and irreversible. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:407-413 [Conf]
  5. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
    A True Single-Phase 8-bit Adiabatic Multiplier. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:758-763 [Conf]
  6. Kumar N. Lalgudi, Marios C. Papaefthymiou
    DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:304-309 [Conf]
  7. Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak
    Optimizing Systems for Effective Block-Processing: The k-Delay Problem. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:714-719 [Conf]
  8. Xun Liu, Marios C. Papaefthymiou
    Design of a high-throughput low-power IS95 Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:263-268 [Conf]
  9. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Maximizing Performance by Retiming and Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:231-236 [Conf]
  10. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    Practical repeater insertion for low power: what repeater library do we need? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:30-35 [Conf]
  11. Marios C. Papaefthymiou, Keith H. Randall
    TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:497-502 [Conf]
  12. Xun Liu, Marios C. Papaefthymiou
    A static power estimation methodolodgy for IP-based design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:280-289 [Conf]
  13. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:643-649 [Conf]
  14. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1330-1335 [Conf]
  15. Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
    Reduced Delay Uncertainty in High Performance Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10068-10075 [Conf]
  16. Zhentao Yu, Marios C. Papaefthymiou, Xun Liu
    Skew spreading for peak current reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:461-464 [Conf]
  17. Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
    Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:74-81 [Conf]
  18. Giuseppe Bernacchia, Marios C. Papaefthymiou
    Analytical macromodeling for high-level power estimation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:280-283 [Conf]
  19. Xun Liu, Marios C. Papaefthymiou
    A Markov chain sequence generator for power macromodeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:404-411 [Conf]
  20. Marios C. Papaefthymiou
    Asymptotically efficient retiming under setup and hold constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:396-401 [Conf]
  21. Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab
    An Algorithm for Geometric Load Balancing with Two Constraints. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  22. Jiyoun Kim, Marios C. Papaefthymiou, José Neves
    Parallelizing post-placement timing optimization. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  23. Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou
    A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:422-425 [Conf]
  24. Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
    Empirical evaluation of timing and power in resonant clock distribution. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:249-252 [Conf]
  25. Xun Liu, Marios C. Papaefthymiou
    Incorporation of input glitches into power macromodeling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:846-849 [Conf]
  26. Joohee Kim, Marios C. Papaefthymiou
    Constant-load energy recovery memory for efficient high-speed operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:240-243 [Conf]
  27. Suhwan Kim, Marios C. Papaefthymiou
    True single-phase energy-recovering logic for low-power, high-speed VLSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:167-172 [Conf]
  28. Suhwan Kim, Marios C. Papaefthymiou
    Single-phase source-coupled adiabatic logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:97-99 [Conf]
  29. Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
    Energy recovering static memory. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:92-97 [Conf]
  30. Marios C. Papaefthymiou, Kumar N. Lalgudi
    Fixed-phase retiming for low power design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:259-264 [Conf]
  31. Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
    A GHz-class charge recovery logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:91-94 [Conf]
  32. Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
    A resonant clock generator for single-phase adiabatic systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:159-164 [Conf]
  33. Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou
    A 225 MHz resonant clocked ASIC chip. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:48-53 [Conf]
  34. Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler
    Two-Phase Resonant Clock Distribution. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:65-70 [Conf]
  35. Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
    Experimental Evaluation of Resonant Clock Distribution. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:135-140 [Conf]
  36. Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
    Boost Logic: A High Speed Energy Recovery Circuit Family. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:22-27 [Conf]
  37. Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou
    Energy Recovering ASIC Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:133-138 [Conf]
  38. Fang Wang, Hubertus Franke, Marios C. Papaefthymiou, Pratap Pattnaik, Larry Rudolph, Mark S. Squillante
    A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. [Citation Graph (0, 0)][DBLP]
    JSSPP, 1996, pp:111-125 [Conf]
  39. Fang Wang, Marios C. Papaefthymiou, Mark S. Squillante
    Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. [Citation Graph (0, 0)][DBLP]
    JSSPP, 1997, pp:277-298 [Conf]
  40. Anant Agarwal, John V. Guttag, Christoforos N. Hadjicostis, Marios C. Papaefthymiou
    Memory Assignment for Multiprocessor Caches through Grey Coloring. [Citation Graph (0, 0)][DBLP]
    PARLE, 1994, pp:351-362 [Conf]
  41. Joohee Kim, Marios C. Papaefthymiou
    Dynamic Memory Design for Low Data-Retention Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:207-216 [Conf]
  42. Jiyoun Kim, José Neves, Marios C. Papaefthymiou
    Multi-Session Partitioning for Parallel Timing Optimization. [Citation Graph (0, 0)][DBLP]
    PDCAT, 2005, pp:598-602 [Conf]
  43. Marios C. Papaefthymiou
    Understanding Retiming Through Maximum Average-Weight Cycles. [Citation Graph (0, 0)][DBLP]
    SPAA, 1991, pp:338-348 [Conf]
  44. Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou
    An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. [Citation Graph (0, 0)][DBLP]
    SPAA, 1996, pp:89-98 [Conf]
  45. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
    Fine-grain real-time reconfigurable pipelining. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:599-610 [Journal]
  46. Kumar N. Lalgudi, Marios C. Papaefthymiou
    Computing Strictly-Second Shortest Paths. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1997, v:63, n:4, pp:177-181 [Journal]
  47. Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou
    Optimizing two-phase, level-clocked circuitry. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1997, v:44, n:1, pp:148-199 [Journal]
  48. Marios C. Papaefthymiou
    Understanding Retiming Through Maximum Avarage-Delay Cycles. [Citation Graph (0, 0)][DBLP]
    Mathematical Systems Theory, 1994, v:27, n:1, pp:65-84 [Journal]
  49. Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou
    Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems. [Citation Graph (0, 0)][DBLP]
    Perform. Eval., 1996, v:27, n:4, pp:273-296 [Journal]
  50. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
    Charge-Recovery Computing on Silicon. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:651-659 [Journal]
  51. Kumar N. Lalgudi, Marios C. Papaefthymiou
    Retiming edge-triggered circuits under general delay models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1393-1408 [Journal]
  52. Farinaz Koushanfar, Darko Kirovski, Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou
    Symbolic debugging of embedded hardware and software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:392-401 [Journal]
  53. Xun Liu, Marios C. Papaefthymiou
    A Markov chain sequence generator for power macromodeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1048-1062 [Journal]
  54. Xun Liu, Marios C. Papaefthymiou
    HyPE: hybrid power estimation for IP-based systems-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1089-1103 [Journal]
  55. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Retiming and clock scheduling for digital circuit optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:184-203 [Journal]
  56. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    Practical repeater insertion for low power: what repeater library do we need? [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:917-924 [Journal]
  57. Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak
    Optimizing computations for effective block-processing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:604-630 [Journal]
  58. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
    RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  59. Mazhar Alidina, J. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
    Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:426-436 [Journal]
  60. Suhwan Kim, Marios C. Papaefthymiou
    True single-phase adiabatic circuitry. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:52-63 [Journal]
  61. Joohee Kim, Marios C. Papaefthymiou
    Block-based multiperiod dynamic memory design for low data-retention power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1006-1018 [Journal]
  62. Xun Liu, Marios C. Papaefthymiou
    Design of a 20-mb/s 256-state Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:965-975 [Journal]
  63. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
    A true single-phase energy-recovery multiplier. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:194-207 [Journal]

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