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Erik Brunvand: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Erik Brunvand
    Low latency self-timed flow-through FIFOs. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:76-90 [Conf]
  2. Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva
    High-Level Asynchronous System Design Using the ACK Framework. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:93-103 [Conf]
  3. Ajay Khoche, Erik Brunvand
    Testing self-timed circuits using partial scan. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:160-169 [Conf]
  4. Sandeep Pagey, Ajay Khoche, Erik Brunvand
    DFT for fast testing of self-timed control circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:382-386 [Conf]
  5. Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
    Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:104-109 [Conf]
  6. Erik Brunvand
    Using FPLs to Prototoype a Self-Timed Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:192-198 [Conf]
  7. Gaurav Gulati, Erik Brunvand
    Design of a cell library for asynchronous microengines. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:385-389 [Conf]
  8. Dave Nellans, Vamshi Krishna Kadaru, Erik Brunvand
    ARCS: an architectural level communication driven simulator. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:73-77 [Conf]
  9. Jung-Lin Yang, Erik Brunvand
    Using dynamic domino circuits in self-timed systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:253-256 [Conf]
  10. Jae-Tack Yoo, Erik Brunvand, Kent F. Smith
    Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:148-151 [Conf]
  11. John B. Carter, Wilson C. Hsieh, Leigh Stoller, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael Parker, Lambert Schaelicke, Terry Tateyama
    Impulse: Building a Smarter Memory Controller. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:70-79 [Conf]
  12. Erik Brunvand, Nick Michell, Kent F. Smith
    A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:76-80 [Conf]
  13. Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
    Practical Advances in Asynchronous Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:662-668 [Conf]
  14. Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand
    Peephole Optimization of Asynchronous Macromodule Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:442-446 [Conf]
  15. Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella
    Performance Analysis and Optimization of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:221-224 [Conf]
  16. William F. Richardson, Erik Brunvand
    Precise exception handling for a self-timed processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:32-37 [Conf]
  17. Jung-Lin Yang, Erik Brunvand
    Self-Timed Design with Dynamic Domino Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:217-219 [Conf]
  18. Ajay Khoche, Erik Brunvand
    ACT: A DFT Tool for Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:829-837 [Conf]
  19. John B. Carter, Wilson C. Hsieh, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael Parker, Lambert Schaelicke, Leigh Stoller, Terry Tateyama
    Memory System Support for Irregular Applications. [Citation Graph (0, 0)][DBLP]
    LCR, 1998, pp:17-26 [Conf]
  20. Erik Brunvand, M. Starkey
    An Integrated Environment for the Design and Simulation of Self-Timed Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:137-146 [Conf]
  21. Ajay Khoche, Erik Brunvand
    A partial scan methodology for testing self-timed circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:283-289 [Conf]
  22. Ajay Khoche, Erik Brunvand
    Critical hazard free test generation for asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:203-209 [Conf]
  23. Ganesh Gopalakrishnan, Erik Brunvand, Nick Michell, Steven M. Nowick
    A correctness criterion for asynchronous circuit validation and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:11, pp:1309-1318 [Journal]
  24. V. Chandramouli, Erik Brunvand, Kent F. Smith
    Self-Timed Design in GaAs - Case Study of a High-Speed, Parallel Multiplier. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:146- [Journal]
  25. Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand
    Peephole optimization of asynchronous macromodule networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:30-37 [Journal]

  26. Hardware-accelerated gradient noise for graphics. [Citation Graph (, )][DBLP]


  27. Hardware prediction of OS run-length for fine-grained resource customization. [Citation Graph (, )][DBLP]


  28. TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing. [Citation Graph (, )][DBLP]


  29. Fast ray tracing and the potential effects on graphics and gaming courses. [Citation Graph (, )][DBLP]


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