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Chris J. Myers :
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Hiroshi Saito , Nattha Jindapetch , Tomohiro Yoneda , Chris J. Myers , Takashi Nanya ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. [Citation Graph (0, 0)][DBLP ] CIT, 2006, pp:172- [Conf ] Allen E. Sjogren , Chris J. Myers Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. [Citation Graph (0, 0)][DBLP ] ARVLSI, 1997, pp:47-61 [Conf ] Chris Winstead , Jie Dai , Woo Jin Kim , Scott Little , Yong-Bin Kim , Chris J. Myers , Christian Schlegel Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. [Citation Graph (0, 0)][DBLP ] ARVLSI, 2001, pp:132-147 [Conf ] Kip C. Killpack , Eric Mercer , Chris J. Myers A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. [Citation Graph (0, 0)][DBLP ] ARVLSI, 2001, pp:188-201 [Conf ] Chris J. Myers , Tomas Rokicki , Teresa H. Y. Meng Automatic synthesis of gate-level timed circuits with choice. [Citation Graph (0, 0)][DBLP ] ARVLSI, 1995, pp:42-58 [Conf ] Chris J. Myers , Wendy Belluomini , Kip Kallpack , Eric Peskin , Hao Zheng Timed circuits: a new paradigm for high-speed design. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2001, pp:335-340 [Conf ] Wendy Belluomini , Chris J. Myers Efficient Timing Analysis Algorithms for Timed State Space Exploration. [Citation Graph (0, 0)][DBLP ] ASYNC, 1997, pp:88-100 [Conf ] Wendy Belluomini , Chris J. Myers , H. Peter Hofstee Verification of Delayed-Reset Domino Circuits Using ATACS. [Citation Graph (0, 0)][DBLP ] ASYNC, 1999, pp:3-12 [Conf ] Wei-Chun Chou , Peter A. Beerel , Ran Ginosar , Rakefet Kol , Chris J. Myers , Shai Rotem , Ken S. Stevens , Kenneth Y. Yun Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP ] ASYNC, 1998, pp:80-0 [Conf ] Nam-Phuong D. Nguyen , Hiroyuki Kuwahara , Chris J. Myers , James P. Keener The Design of a Genetic Muller C-Element. [Citation Graph (0, 0)][DBLP ] ASYNC, 2007, pp:95-104 [Conf ] Chris J. Myers , Peter A. Beerel , Teresa H. Y. Meng Technology mapping of timed circuits. [Citation Graph (0, 0)][DBLP ] ASYNC, 1995, pp:138-0 [Conf ] Chris J. Myers , Hans M. Jacobson Efficient Exact Two-Level Hazard-Free Logic Minimization. [Citation Graph (0, 0)][DBLP ] ASYNC, 2001, pp:64-73 [Conf ] Tomohiro Yoneda , Atsushi Matsumoto , Manabu Kato , Chris J. Myers High Level Synthesis of Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] ASYNC, 2005, pp:178-189 [Conf ] Tomohiro Yoneda , Hiroomi Onda , Chris J. Myers Synthesis of Speed Independent Circuits Based on Decomposition. [Citation Graph (0, 0)][DBLP ] ASYNC, 2004, pp:135-145 [Conf ] Shai Rotem , Ken S. Stevens , Charles Dike , Marly Roncken , Boris Agapiev , Ran Ginosar , Rakefet Kol , Peter A. Beerel , Chris J. Myers , Kenneth Y. Yun RAPPID: An Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP ] ASYNC, 1999, pp:60-70 [Conf ] Bin Zhou , Tomohiro Yoneda , Chris J. Myers Framework of Timed Trace Theoretic Verification Revisited. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2001, pp:437-442 [Conf ] Denduang Pradubsuwun , Tomohiro Yoneda , Chris J. Myers Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. [Citation Graph (0, 0)][DBLP ] ATVA, 2004, pp:339-353 [Conf ] Tomohiro Yoneda , Chris J. Myers Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] ATVA, 2006, pp:229-244 [Conf ] Scott Little , David Walter , Nicholas Seegmiller , Chris J. Myers , Tomohiro Yoneda Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. [Citation Graph (0, 0)][DBLP ] ATVA, 2004, pp:426-440 [Conf ] Hiroyuki Kuwahara , Chris J. Myers , Michael S. Samoilov Abstracted Stochastic Analysis of Type 1 Pili Expression in E.coli. [Citation Graph (0, 0)][DBLP ] BIOCOMP, 2006, pp:125-134 [Conf ] Wendy Belluomini , Chris J. Myers Verification of Timed Systems Using POSETs. [Citation Graph (0, 0)][DBLP ] CAV, 1998, pp:403-415 [Conf ] Tomas Rokicki , Chris J. Myers Automatic Verification of Timed Circuits. [Citation Graph (0, 0)][DBLP ] CAV, 1994, pp:468-480 [Conf ] Tomohiro Yoneda , Tomoya Kitai , Chris J. Myers Automatic Derivation of Timing Constraints by Failure Analysis. [Citation Graph (0, 0)][DBLP ] CAV, 2002, pp:195-208 [Conf ] Hao Zheng , Eric Mercer , Chris J. Myers Automatic Abstraction for Verification of Timed Circuits and Systems. [Citation Graph (0, 0)][DBLP ] CAV, 2001, pp:182-193 [Conf ] Hans M. Jacobson , Chris J. Myers , Ganesh Gopalakrishnan Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. [Citation Graph (0, 0)][DBLP ] ICCAD, 2000, pp:303-310 [Conf ] Sung Tae Jung , Chris J. Myers Direct synthesis of timed asynchronous circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:332-338 [Conf ] Curtis A. Nelson , Chris J. Myers , Tomohiro Yoneda Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:424-432 [Conf ] Scott Little , Nicholas Seegmiller , David Walter , Chris J. Myers , Tomohiro Yoneda Verification of analog/mixed-signal circuits using labeled hybrid petri nets. [Citation Graph (0, 0)][DBLP ] ICCAD, 2006, pp:275-282 [Conf ] Brandon M. Bachman , Hao Zheng , Chris J. Myers Architectural Synthesis of Timed Asynchronous Systems. [Citation Graph (0, 0)][DBLP ] ICCD, 1999, pp:354-363 [Conf ] Chris J. Myers , Teresa H. Y. Meng Synthesis of Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:279-284 [Conf ] Hao Zheng , Chris J. Myers , David Walter , Scott Little , Tomohiro Yoneda Verification of Timed Circuits with Failure Directed Abstractions. [Citation Graph (0, 0)][DBLP ] ICCD, 2003, pp:28-35 [Conf ] Nathan Barker , Chris J. Myers , Hiroyuki Kuwahara Learning Genetic Regulatory Network Connectivity from Time Series Data. [Citation Graph (0, 0)][DBLP ] IEA/AIE, 2006, pp:962-971 [Conf ] Jie Dai , C. J. Winstead , Chris J. Myers , Reid R. Harrison , Christian Schlegel Cell library for automatic synthesis of analog error control decoders. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2002, pp:481-484 [Conf ] Tomoya Kitai , Yusuke Oguro , Tomohiro Yoneda , Eric Mercer , Chris J. Myers Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. [Citation Graph (0, 0)][DBLP ] PRDC, 2002, pp:210-220 [Conf ] Hiroyuki Kuwahara , Chris J. Myers Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions. [Citation Graph (0, 0)][DBLP ] RECOMB, 2007, pp:166-180 [Conf ] Robert Thacker , Wendy Belluomini , Chris J. Myers Timed Circuit Synthesis Using Implicit Methods. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:181-188 [Conf ] Eric Mercer , Chris J. Myers , Tomohiro Yoneda Modular Synthesis of Timed Circuits using Partial Order Reduction. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Chris J. Myers , Reid R. Harrison , David Walter , Nicholas Seegmiller , Scott Little The Case for Analog Circuit Verification. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2006, v:153, n:3, pp:53-63 [Journal ] Peter A. Beerel , Chris J. Myers , Teresa H. Y. Meng Covering conditions and algorithms for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:205-219 [Journal ] Wendy Belluomini , Chris J. Myers Timed state space exploration using POSETs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:501-520 [Journal ] Wendy Belluomini , Chris J. Myers , H. Peter Hofstee Timed circuit verification using TEL structures. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:129-146 [Journal ] Hans M. Jacobson , Chris J. Myers Efficient algorithms for exact two-level hazard-free logic minimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1269-1283 [Journal ] Sung Tae Jung , Chris J. Myers Direct synthesis of timed circuits from free-choice STGs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:275-290 [Journal ] Chris J. Myers , Tomas Rokicki , Teresa H. Y. Meng POSET timing and its application to the synthesis and verification of gate-level timed circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:769-786 [Journal ] Hao Zheng , Eric Mercer , Chris J. Myers Modular verification of timed circuits using automatic abstraction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1138-1153 [Journal ] Hao Zheng , Chris J. Myers , David Walter , Scott Little , Tomohiro Yoneda Verification of timed circuits with failure-directed abstractions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:403-412 [Journal ] Hiroyuki Kuwahara , Chris J. Myers , Michael S. Samoilov , Nathan A. Barker , Adam P. Arkin Automated Abstraction Methodology for Genetic Regulatory Networks. [Citation Graph (0, 0)][DBLP ] , 2006, v:, n:, pp:150-175 [Journal ] Frédéric Béal , Tomohiro Yoneda , Chris J. Myers Hazard Checking of Timed Asynchronous Circuits Revisited. [Citation Graph (0, 0)][DBLP ] ACSD, 2007, pp:51-60 [Conf ] Scott Little , David Walter , Kevin Jones , Chris Myers Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. [Citation Graph (0, 0)][DBLP ] ATVA, 2007, pp:114-128 [Conf ] David Walter , Scott Little , Chris Myers Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. [Citation Graph (0, 0)][DBLP ] ATVA, 2007, pp:66-81 [Conf ] Chris J. Myers , Teresa H. Y. Meng Synthesis of timed asynchronous circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:106-119 [Journal ] Allen E. Sjogren , Chris J. Myers Interfacing synchronous and asynchronous modules within a high-speed pipeline. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:573-583 [Journal ] A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). [Citation Graph (, )][DBLP ] Symbolic Model Checking of Analog/Mixed-Signal Circuits. [Citation Graph (, )][DBLP ] Genetic design automation. [Citation Graph (, )][DBLP ] Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. [Citation Graph (, )][DBLP ] iBioSim: a tool for the analysis and design of genetic circuits. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.458secs