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Title:
Author:
Carl Sechen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ted Stanion, Carl Sechen
    Quasi-algebraic decompositions of switching functions. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:358-367 [Conf]
  2. Sheng Sun, Larry McMurchie, Carl Sechen
    A High-Performance 64-bit Adder Implemented in Output Prediction Logic. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:213-223 [Conf]
  3. Martin Lefebvre, David Marple, Carl Sechen
    The Future of Custom Cell Generation in Physical Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:446-451 [Conf]
  4. Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
    Panel: (When) Will FPGAs Kill ASICs? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:321-322 [Conf]
  5. Carl Sechen
    Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:73-80 [Conf]
  6. Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar
    Libraries: lifejacket or straitjacket. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:642-643 [Conf]
  7. Carl Sechen, Alberto L. Sangiovanni-Vincentelli
    TimberWolf3.2: a new standard cell placement and global routing package. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:432-439 [Conf]
  8. Ted Stanion, Carl Sechen
    A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:60-64 [Conf]
  9. William Swartz, Carl Sechen
    Timing Driven Placement for Large Standard Cell Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:211-215 [Conf]
  10. Hiran Tennakoon, Carl Sechen
    Efficient and accurate gate sizing with piecewise convex delay models. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:807-812 [Conf]
  11. Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
    Timing and Crosstalk Driven Area Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:378-381 [Conf]
  12. Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen
    Efficient timing closure without timing driven placement and routing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:268-273 [Conf]
  13. Jovanka Ciric, Gin Yee, Carl Sechen
    Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:277-282 [Conf]
  14. Tatjana Serdar, Carl Sechen
    Automatic datapath tile placement and routing. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:552-559 [Conf]
  15. Kalapi Roy-Neogi, Carl Sechen
    Multiple FPGA Partitioning with Performance Optimization. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:146-152 [Conf]
  16. Jovanka Ciric, Carl Sechen
    Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:610-617 [Conf]
  17. Larry McMurchie, Carl Sechen
    WTA: waveform-based timing analysis for deep submicron circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:625-631 [Conf]
  18. Tatjana Serdar, Carl Sechen
    AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:91-97 [Conf]
  19. Ted Stanion, Carl Sechen
    Maximum projections of don't care conditions in a Boolean network. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:674-679 [Conf]
  20. Wern-Jieh Sun, Carl Sechen
    Efficient and effective placement for very large circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:170-177 [Conf]
  21. Wern-Jieh Sun, Carl Sechen
    A loosely coupled parallel algorithm for standard cell placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:137-144 [Conf]
  22. William Swartz, Carl Sechen
    New Algorithms for the Placement and Routing of Macro Cells. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:336-339 [Conf]
  23. William Swartz, Carl Sechen
    A new generalized row-based global router. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:491-498 [Conf]
  24. Hiran Tennakoon, Carl Sechen
    Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:395-402 [Conf]
  25. Tyler Thorp, Gin Yee, Carl Sechen
    Domino logic synthesis using complex static gates. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:242-247 [Conf]
  26. Miodrag Vujkovic, Carl Sechen
    Optimized power-delay curve generation for standard cell ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:387-394 [Conf]
  27. Qicheng Yu, Carl Sechen
    Approximate symbolic analysis of large analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:664-671 [Conf]
  28. Bingzhong Guan, Carl Sechen
    Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:378-383 [Conf]
  29. Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen
    Output Prediction Logic: A High-Performance CMOS Design Technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:247-0 [Conf]
  30. Tyler Thorp, Gin Yee, Carl Sechen
    Design and Synthesis of Monotonic Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:569-572 [Conf]
  31. Gin Yee, Carl Sechen
    Clock-Delayed Domino for Adder and Combinational Logic Desig. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:332-0 [Conf]
  32. Jer-Jaw Hsu, Carl Sechen
    Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2083-2087 [Conf]
  33. Su Kio, Kian Haur Chong, Carl Sechen
    A low power delayed-clocks generation and distribution system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:445-448 [Conf]
  34. Qicheng Yu, Carl Sechen
    Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2088-2091 [Conf]
  35. Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen
    Chip-level area routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:197-204 [Conf]
  36. Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen
    An Automated Shielding Algorithm and Tool For Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:369-374 [Conf]
  37. Xinyu Guo, Carl Sechen
    High Speed Redundant Adder and Divider in Output Prediction Logic. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:34-41 [Conf]
  38. Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen
    409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:52-58 [Conf]
  39. Miodrag Vujkovic, Carl Sechen
    Optimized Power-Delay Curve Generation for Standard Cell ICs. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:413-418 [Conf]
  40. Miodrag Vujkovic, David Wadkins, Carl Sechen
    Efficient Post-layout Power-Delay Curve Generation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:393-403 [Conf]
  41. Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen
    A Sea-of-Gates Style FPGA Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:221-224 [Conf]
  42. Jovanka Ciric, Carl Sechen
    Efficient canonical form for Boolean matching of complex functions in large libraries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:535-544 [Journal]
  43. Le-Chin Eugene Liu, Carl Sechen
    Multilayer pin assignment for macro cell circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1452-1461 [Journal]
  44. Le-Chin Eugene Liu, Carl Sechen
    Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1442-1451 [Journal]
  45. Qicheng Yu, Carl Sechen
    Efficient approximation of symbolic network functions using matroid intersection algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1073-1081 [Journal]
  46. Ted Stanion, Debashis Bhattacharya, Carl Sechen
    An efficient method for generating exhaustive test sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1516-1525 [Journal]
  47. Ted Stanion, Carl Sechen
    Boolean division and factorization using binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1179-1184 [Journal]
  48. Wern-Jieh Sun, Carl Sechen
    Efficient and effective placement for very large circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:349-359 [Journal]
  49. Wern-Jieh Sun, Carl Sechen
    A parallel standard cell placement algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1342-1357 [Journal]
  50. Hsiao-Ping Tseng, Carl Sechen
    A gridless multilayer router for standard cell circuits using CTMcells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1462-1479 [Journal]
  51. Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
    Timing- and crosstalk-driven area routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:528-544 [Journal]
  52. Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen
    Post-layout energy-delay analysis of parallel multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  53. Gin Yee, Carl Sechen
    Clock-delayed domino for dynamic circuit design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:425-430 [Journal]
  54. G. N. Hoyer, Gin Yee, Carl Sechen
    Locally clocked pipelines and dynamic logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:58-62 [Journal]

  55. Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. [Citation Graph (, )][DBLP]


  56. A gridless multi-layer router for standard cell circuits using CTM cells. [Citation Graph (, )][DBLP]


  57. Post-layout comparison of high performance 64b static adders in energy-delay space. [Citation Graph (, )][DBLP]


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