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Title:
Author:
Abhijit Chatterjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sudip Chakrabarti, Abhijit Chatterjee
    Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:327-341 [Conf]
  2. Ramakrishna Voorakaranam, Abhijit Chatterjee
    Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:342-357 [Conf]
  3. Huy Nguyen, Abhijit Chatterjee
    OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:258-271 [Conf]
  4. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Low-power domino circuits using NMOS pull-up on off-critical paths. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:533-538 [Conf]
  5. Soumendu Bhattacharya, Abhijit Chatterjee
    A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:68-73 [Conf]
  6. Sasikumar Cherubal, Abhijit Chatterjee
    Test generation for fault isolation in analog circuits using behavioral models. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:19-24 [Conf]
  7. Alfred V. Gomes, Abhijit Chatterjee
    Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:411-416 [Conf]
  8. Achintya Halder, Abhijit Chatterjee
    Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:344-0 [Conf]
  9. Achintya Halder, Abhijit Chatterjee
    Low-cost Production Test of BER for Wireless Receivers. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:64-69 [Conf]
  10. Donghoon Han, Abhijit Chatterjee
    Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:420-425 [Conf]
  11. Donghoon Han, Abhijit Chatterjee
    Robust Built-In Test of RF ICs Using Envelope Detectors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:2-7 [Conf]
  12. Biranchinath Sahu, Abhijit Chatterjee
    Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:405-410 [Conf]
  13. Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterjee
    Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:302-307 [Conf]
  14. Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa
    IC Reliability Simulator ARET and Its Application in Design-for-Reliability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:18-23 [Conf]
  15. Chung-Seok (Andy) Seo, Abhijit Chatterjee, Timothy J. Drabik
    Optically Interconnected Intelligent RAM Multiprocessor: Gigascale Opto-IRAM. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2004, pp:256-260 [Conf]
  16. Chung-Seok (Andy) Seo, Abhijit Chatterjee, Timothy J. Drabik, Behnam S. Arad, Reena Patel
    Prototyping an Embedded Bus-Based Parallel System. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2005, pp:314-319 [Conf]
  17. Abhijit Chatterjee, Richard I. Hartley
    A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:36-39 [Conf]
  18. Abhijit Chatterjee, Rabindra K. Roy
    An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:343-348 [Conf]
  19. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    DRAFTS: Discretized Analog Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:509-514 [Conf]
  20. Pankaj Pant, Vivek De, Abhijit Chatterjee
    Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:403-408 [Conf]
  21. Sasikumar Cherubal, Abhijit Chatterjee
    Test generation based diagnosis of device parameters for analog circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:596-602 [Conf]
  22. Sasikumar Cherubal, Abhijit Chatterjee
    Parametric Fault Diagnosis for Analog Systems Using Functional Mapping. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:195-0 [Conf]
  23. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
    Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:288-293 [Conf]
  24. Alfred V. Gomes, Abhijit Chatterjee
    Minimal Length Diagnostic Tests for Analog Circuits using Test History. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:189-194 [Conf]
  25. Ganesh Srinivasan, Soumendu Bhattacharya, Sasikumar Cherubal, Abhijit Chatterjee
    Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefit. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:280-285 [Conf]
  26. Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee
    Online RF checkers for diagnosing multi-gigahertz automatic test boards on low cost ATE platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:658-663 [Conf]
  27. Ramakrishna Voorakaranam, Sasikumar Cherubal, Abhijit Chatterjee
    A Signature Test Framework for Rapid Production Testing of RF Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:186-191 [Conf]
  28. Soumendu Bhattacharya, Abhijit Chatterjee
    Constrained Specification-Based Test Stimulus Generation for Analog Circuits Using Nonlinear Performance Prediction Models. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:25-32 [Conf]
  29. Soumendu Bhattacharya, Ganesh Srinivasan, Sasikumar Cherubal, Abhijit Chatterjee
    Test Time Reduction for ACPR Measurement of Wireless Transceivers Using Periodic Bit-Stream Sequences. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:372-377 [Conf]
  30. Sasikumar Cherubal, Abhijit Chatterjee
    A Methodology for Efficient Simulation and Diagnosis of Mixed-Signal Systems Using Error Waveforms. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:357-0 [Conf]
  31. Alfred V. Gomes, Ramakrishna Voorakaranam, Abhijit Chatterjee
    Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:341-348 [Conf]
  32. Pramodchandran N. Variyam, Abhijit Chatterjee
    Specification-Driven Test Design for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:335-340 [Conf]
  33. Xiangdong Xuan, Abhijit Chatterjee
    Sensitivity and Reliability Evaluation for Mixed-Signal ICs under Electromigration and Hot-Carrier Effects. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:323-328 [Conf]
  34. Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
    Adaptive Design for Performance-Optimized Robustness. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:3-11 [Conf]
  35. Abhijit Chatterjee, Manuel A. d'Abreu
    Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:136-143 [Conf]
  36. Chung-Seok (Andy) Seo, Abhijit Chatterjee, Sang-Yeon Cho, Nan M. Jokerst
    Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:292-297 [Conf]
  37. Abhijit Chatterjee
    Application of the Reactivity Index to Propose Intra and Intermolecular Reactivity in Catalytic Materials. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (3), 2006, pp:77-81 [Conf]
  38. Sudip Chakrabarti, Abhijit Chatterjee
    Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:562-567 [Conf]
  39. Abhijit Chatterjee, Jacob A. Abraham
    RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:340-343 [Conf]
  40. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin Sean Lee
    Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:693-700 [Conf]
  41. Alfred V. Gomes, Abhijit Chatterjee
    Robust optimization based backtrace method for analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:304-308 [Conf]
  42. Junwei Hou, Abhijit Chatterjee
    CONCERT: a concurrent transient fault simulator for nonlinear analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:384-391 [Conf]
  43. Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
    Fault-based automatic test generator for linear analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:88-91 [Conf]
  44. Pankaj Pant, Abhijit Chatterjee
    Efficient diagnosis of path delay faults in digital logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:471-476 [Conf]
  45. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
    Synthesis of BIST hardware for performance testing of MCM interconnections. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:69-73 [Conf]
  46. Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu
    Automatic test generation for linear digital systems with bi-level search using matrix transform methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:224-228 [Conf]
  47. Pramodchandran N. Variyam, Abhijit Chatterjee
    Test generation for comprehensive testing of linear analog circuits using transient response sampling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:382-385 [Conf]
  48. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
    A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:567-573 [Conf]
  49. Abhijit Chatterjee
    A New Approach to Fault-Tolerance in Linear Analog Systems Based on Checksum-Coded State Space Representations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:478-481 [Conf]
  50. Abhijit Chatterjee, Rabindra K. Roy
    Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:606-609 [Conf]
  51. Abhijit Chatterjee, Manuel A. d'Abreu
    Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:212-215 [Conf]
  52. Junwei Hou, Abhijit Chatterjee
    Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:35-41 [Conf]
  53. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    MIXER: Mixed-Signal Fault Simulator. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:568-571 [Conf]
  54. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    A Signature Analyzer for Analog and Mixed-signal Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:284-287 [Conf]
  55. Rajesh Pendurkar, Abhijit Chatterjee, Craig A. Tovey
    Optimal single probe traversal algorithm for testing of MCM substrat. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:396-0 [Conf]
  56. Chung-Seok (Andy) Seo, Abhijit Chatterjee
    A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:24-29 [Conf]
  57. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Sizing CMOS Circuits for Increased Transient Error Tolerance. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:11-16 [Conf]
  58. Huy Nguyen, Abhijit Chatterjee
    Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:61-0 [Conf]
  59. Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt
    On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST). [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:106-111 [Conf]
  60. José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
    On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:23-28 [Conf]
  61. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra
    Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:35-40 [Conf]
  62. Junwei Hou, William H. Kao, Abhijit Chatterjee
    A novel concurrent fault simulation method for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:448-451 [Conf]
  63. Kyu-won Choi, Abhijit Chatterjee
    HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:207-212 [Conf]
  64. Kyu-won Choi, Abhijit Chatterjee
    UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:72-77 [Conf]
  65. Achintya Halder, Abhijit Chatterjee
    Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:401-406 [Conf]
  66. Chung-Seok (Andy) Seo, Abhijit Chatterjee, Nan M. Jokerst
    This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:567-572 [Conf]
  67. Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy
    System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:225-230 [Conf]
  68. Kyu-won Choi, Abhijit Chatterjee
    Efficient instruction-level optimization methodology for low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:147-152 [Conf]
  69. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee
    An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:173-182 [Conf]
  70. Soumendu Bhattacharya, Abhijit Chatterjee
    Use of Embedded Sensors for Built-In-Test of RF Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:801-809 [Conf]
  71. Sudip Chakrabarti, Abhijit Chatterjee
    On-line fault detection in DSP circuits using extrapolated checksums with minimal test points. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:955-963 [Conf]
  72. Abhijit Chatterjee
    Seamless Research Between Academia And Industry To Facilitate Test Of Integrated High-Speed Wireless Systems: Is This An Illusion? [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1287- [Conf]
  73. Abhijit Chatterjee
    Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:582-591 [Conf]
  74. Sasikumar Cherubal, Abhijit Chatterjee
    Optimal INL/DNL testing of A/D converters using a linear model. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:358-366 [Conf]
  75. Sasikumar Cherubal, Abhijit Chatterjee
    A high-resolution jitter measurement technique using ADC sampling. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:838-847 [Conf]
  76. Achintya Halder, Soumendu Bhattacharya, Abhijit Chatterjee
    Automatic Multitone Alternate Test Generation For RF Circuits Using Behavioral Models. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:665-673 [Conf]
  77. Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan, David E. Schimmel
    A Novel Low-Cost Approach to MCM Interconnect Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:184-192 [Conf]
  78. Bruce C. Kim, David C. Keezer, Abhijit Chatterjee
    A high throughput test methodology for MCM substrates. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:234-0 [Conf]
  79. Pankaj Pant, Abhijit Chatterjee
    Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:245-252 [Conf]
  80. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
    A distributed BIST technique for diagnosis of MCM interconnections. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:214-221 [Conf]
  81. Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee
    Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:252-261 [Conf]
  82. Koppolu Sasidhar, Abhijit Chatterjee, Vinod K. Agarwal, Joseph L. A. Hughes
    Distributed Probabilistic Diagnosis of MCMs on Large Area. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:208-216 [Conf]
  83. Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian
    Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:818-827 [Conf]
  84. Ramakrishna Voorakaranam, Sudip Chakrabarti, Junwei Hou, Alfred V. Gomes, Sasikumar Cherubal, Abhijit Chatterjee, William H. Kao
    Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:903-912 [Conf]
  85. Ramakrishna Voorakaranam, Randy Newby, Sasikumar Cherubal, Bob Cometta, Thomas Kuehl, David M. Majernik, Abhijit Chatterjee
    Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and Results. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1174-1181 [Conf]
  86. Donghoon Han, Abhijit Chatterjee
    Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:127-130 [Conf]
  87. Chung-Seok (Andy) Seo, Abhijit Chatterjee
    Free-Space Optical Interconnect for High-Performance MCM Systems. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:294-298 [Conf]
  88. Kyu-won Choi, Abhijit Chatterjee
    PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:178-187 [Conf]
  89. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Low-power dual Vth pseudo dual Vdd domino circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:273-277 [Conf]
  90. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
    Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:606-612 [Conf]
  91. Soumendu Bhattacharya, Vishwanath Natarajan, Abhijit Chatterjee, Sankar Nair
    Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:729-733 [Conf]
  92. Abhijit Chatterjee, A. Keshavarzi, Amit Patra, Siddhartha Mukhopadhyay
    Test Methodologies in the Deep Submicron Era -- Analog, Mixed-Signal, and RF. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:12-13 [Conf]
  93. Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi
    Low-cost DC built-in self-test of linear analog circuits using checksums. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:230-233 [Conf]
  94. Abhijit Chatterjee, Rabindra K. Roy
    Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:265-270 [Conf]
  95. Abhijit Chatterjee, Naveena Nagi
    Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:388-392 [Conf]
  96. Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
    Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:154-159 [Conf]
  97. Sasikumar Cherubal, Abhijit Chatterjee
    An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:550-555 [Conf]
  98. Sasikumar Cherubal, Ramakrishna Voorakaranam, Abhijit Chatterjee, John McLaughlin, Jason L. Smith, David M. Majernik
    Concurrent RF Test Using Optimized Modulated RF Stimuli. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1017-1022 [Conf]
  99. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:159-164 [Conf]
  100. Achintya Halder, Soumendu Bhattacharya, Ganesh Srinivasan, Abhijit Chatterjee
    A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:289-294 [Conf]
  101. Achintya Halder, Abhijit Chatterjee
    Low-Cost Production Testing of Wireless Transmitters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:437-442 [Conf]
  102. Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
    Efficient multisine testing of analog circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:234-238 [Conf]
  103. Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy
    Impact of Partial Reset on Fault Independent Testing and BIST. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:537-539 [Conf]
  104. Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee
    Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:199-204 [Conf]
  105. Koppolu Sasidhar, Abhijit Chatterjee
    Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:65-68 [Conf]
  106. Pramodchandran N. Variyam, Abhijit Chatterjee
    FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State Representation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:408-412 [Conf]
  107. Sudip Chakrabarti, Abhijit Chatterjee
    Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:518-523 [Conf]
  108. Pramodchandran N. Variyam, Junwei Hou, Abhijit Chatterjee
    Test Generation for Analog Circuits Using Partial Numerical Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:597-602 [Conf]
  109. Manuel d'Arbreu, Abhijit Chatterjee
    Manufacturability of Mixed Signal Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:608- [Conf]
  110. Heebyung Yoon, Abhijit Chatterjee, Joseph L. A. Hughes
    Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:393-397 [Conf]
  111. Maryam Ashouei, Muhammad M. Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril
    Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:711-716 [Conf]
  112. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterj
    Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:208-213 [Conf]
  113. Soumendu Bhattacharya, Abhijit Chatterjee
    High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test Cost. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:89-100 [Conf]
  114. Soumendu Bhattacharya, Abhijit Chatterjee
    Production Test Methods for Measuring 'Out-of-Band' Interference of Ultra Wide Band (UWB) Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:137-142 [Conf]
  115. Soumendu Bhattacharya, Ganesh Srinivasan, Sasikumar Cherubal, Achintya Halder, Abhijit Chatterjee
    System-level Testing of RF Transmitter Specifications Using Optimized Periodic Bitstreams. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:229-236 [Conf]
  116. Selim Sermet Akbay, Abhijit Chatterjee
    Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:273-290 [Conf]
  117. Selim Sermet Akbay, Abhijit Chatterjee
    Built-In Test of RF Components Using Mapped Feature Extraction Sensors. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:243-248 [Conf]
  118. Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham
    Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:354-361 [Conf]
  119. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:298-303 [Conf]
  120. Achintya Halder, Abhijit Chatterjee
    Low-Cost Alternate EVM Test for Wireless Receiver Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:255-260 [Conf]
  121. Achintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley
    Measuring Stray Capacitance on Tester Hardware. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:351-356 [Conf]
  122. Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan
    Low-cost diagnosis of defects in MCM substrate interconnections. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:260-265 [Conf]
  123. Vishwanath Natarajan, Soumendu Bhattacharya, Abhijit Chatterjee
    Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:192-199 [Conf]
  124. Ashwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee
    Prediction of Analog Performance Parameters Using Oscillation Based Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:377-382 [Conf]
  125. Ganesh Srinivasan, Abhijit Chatterjee, Friedrich Taenzler
    Alternate Loop-Back Diagnostic Tests for Wafer-Level Diagnosis of Modern Wireless Transceivers using Spectral Signatures. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:222-227 [Conf]
  126. Pramodchandran N. Variyam, Abhijit Chatterjee
    Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:132-137 [Conf]
  127. Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi
    Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:261-266 [Conf]
  128. Pramodchandran N. Variyam, Junwei Hou, Abhijit Chatterjee
    Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:214-219 [Conf]
  129. Ramakrishna Voorakaranam, Abhijit Chatterjee
    Test Generation for Accurate Prediction of Analog Specifications. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:137-142 [Conf]
  130. Ramakrishna Voorakaranam, Abhijit Chatterjee
    Hierarchical Test Generation for Analog Circuits Using Incremental Test Development. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:296-303 [Conf]
  131. Hyun Choi, Donghoon Han, Abhijit Chatterjee
    Enhanced Resolution Jitter Testing Using Jitter Expansion. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:104-109 [Conf]
  132. Heebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi
    Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:145-151 [Conf]
  133. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee
    Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:125-130 [Conf]
  134. Rajarajan Senguttuvan, Abhijit Chatterjee
    Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:395-400 [Conf]
  135. Abhijit Chatterjee, Kapil Mayawala, Jeremy S. Edwards, Dionisios G. Vlachos
    Time accelerated Monte Carlo simulations of biological networks using the binomial r-leap method. [Citation Graph (0, 0)][DBLP]
    Bioinformatics, 2005, v:21, n:9, pp:2136-2137 [Journal]
  136. Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi
    DC Built-In Self-Test for Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:26-33 [Journal]
  137. Richard I. Hartley, Kenneth Welles II, Michael Hartman, Abhijit Chatterjee, Paul Delano, Barbara Molnar, Colin Rafferty
    A Rapid-Prototyping Environment for Digital-Signal Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1991, v:8, n:2, pp:11-25 [Journal]
  138. Kaushik Roy, Abhijit Chatterjee
    Guest Editors' Introduction: Low-Power VLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:6-7 [Journal]
  139. Koppolu Sasidhar, Leon Alkalai, Abhijit Chatterjee
    Testing NASA's 3D-Stack MCM Space Flight Computer. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:3, pp:44-55 [Journal]
  140. Pramodchandran N. Variyam, Abhijit Chatterjee
    Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:106-115 [Journal]
  141. Abhijit Chatterjee, P. P. Das, Soumendu Bhattacharya
    Visualization in linear programming using parallel coordinates. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1993, v:26, n:11, pp:1725-1736 [Journal]
  142. Abhijit Chatterjee, Jacob A. Abraham
    The Testability of Generalized Counters Under Multiple Faulty Cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:11, pp:1378-1385 [Journal]
  143. Abhijit Chatterjee, Jacob A. Abraham
    Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:10, pp:1133-1148 [Journal]
  144. Abhijit Chatterjee, Rabindra K. Roy
    Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:11, pp:1208-1218 [Journal]
  145. Abhijit Chatterjee, Manuel A. d'Abreu
    The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:7, pp:794-808 [Journal]
  146. Koppolu Sasidhar, Abhijit Chatterjee
    Hierarchical Diagnosis of Identical Units in a System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:2, pp:186-191 [Journal]
  147. Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian
    Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:10, pp:1007-1019 [Journal]
  148. Abhijit Chatterjee, Jacob A. Abraham
    On the C-Testability of Generalized Counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:713-726 [Journal]
  149. Abhijit Chatterjee, Charles F. Machala III, Ping Yang
    A submicron DC MOSFET model for simulation of analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1193-1207 [Journal]
  150. Junwei Hou, Abhijit Chatterjee
    Concurrent transient fault simulation for analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1385-1398 [Journal]
  151. Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham
    Signature analysis for analog and mixed-signal circuit test response compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:540-546 [Journal]
  152. Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian
    Switching activity generation with automated BIST synthesis forperformance testing of interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1143-1158 [Journal]
  153. Rajesh Pendurkar, Craig A. Tovey, Abhijit Chatterjee
    Single-probe traversal optimization for testing of MCM substrate interconnections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1178-1191 [Journal]
  154. Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee
    Path delay fault diagnosis in combinational circuits with implicitfault enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1226-1235 [Journal]
  155. Pramodchandran N. Variyam, Abhijit Chatterjee
    Specification-driven test generation for analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1189-1201 [Journal]
  156. Pramodchandran N. Variyam, Sasikumar Cherubal, Abhijit Chatterjee
    Prediction of analog performance parameters using fast transienttesting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:349-361 [Journal]
  157. Soumendu Bhattacharya, Abhijit Chatterjee
    Optimized wafer-probe and assembled package test design for analog circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:303-329 [Journal]
  158. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:514-524 [Journal]
  159. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1103-1107 [Journal]
  160. Achintya Halder, Abhijit Chatterjee
    Test generation for specification test of analog circuits using efficient test response observation methods. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:820-832 [Journal]
  161. Muhammad M. Nisar, Maryam Ashouei, Abhijit Chatterjee
    Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:173-182 [Conf]
  162. Shalabh Goyal, Abhijit Chatterjee, Mike Atia
    Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:165-172 [Conf]
  163. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee
    Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:35-42 [Conf]
  164. Donghoon Han, Shalabh Goyal, Soumendu Bhattacharya, Abhijit Chatterjee
    Low Cost Parametric Failure Diagnosis of RF Transceivers. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:205-212 [Conf]
  165. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
    Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  166. Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
    Greedy hardware optimization for linear digital circuits using number splitting and refactorization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:423-431 [Journal]
  167. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
    Pseudo Dual Supply Voltage Domino Logic Design. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:145-152 [Journal]
  168. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
    Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:78-95 [Journal]
  169. Soumendu Bhattacharya, Achintya Halder, Ganesh Srinivasan, Abhijit Chatterjee
    Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:323-339 [Journal]
  170. Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee
    Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:471-482 [Journal]
  171. Shalabh Goyal, Abhijit Chatterjee, Michael Purtell
    A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:95-106 [Journal]

  172. Self-Calibrating Embedded RF Down-Conversion Mixers. [Citation Graph (, )][DBLP]


  173. BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search. [Citation Graph (, )][DBLP]


  174. Low Cost Dynamic Test Methodology for High Precision ΣD ADCs. [Citation Graph (, )][DBLP]


  175. Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems. [Citation Graph (, )][DBLP]


  176. Digital bit stream jitter testing using jitter expansion. [Citation Graph (, )][DBLP]


  177. A novel self-healing methodology for RF Amplifier circuits based on oscillation principles. [Citation Graph (, )][DBLP]


  178. BIST assisted wideband digital compensation for MB-UWB transmitters. [Citation Graph (, )][DBLP]


  179. Cognitive self-adaptive computing and communication systems: Test, control and adaptation. [Citation Graph (, )][DBLP]


  180. Rapid prototyping using high density interconnects. [Citation Graph (, )][DBLP]


  181. Fault-based alternate test of RF components. [Citation Graph (, )][DBLP]


  182. VIZOR: Virtually zero margin adaptive RF for ultra low power wireless communication. [Citation Graph (, )][DBLP]


  183. Guided Probabilistic Checksums for Error Control in Low Power Digital-Filters. [Citation Graph (, )][DBLP]


  184. Aggressively voltage overscaled adaptive RF systems using error control at the bit and symbol levels. [Citation Graph (, )][DBLP]


  185. Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. [Citation Graph (, )][DBLP]


  186. Design of process variation tolerant radio frequency low noise amplifier. [Citation Graph (, )][DBLP]


  187. Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. [Citation Graph (, )][DBLP]


  188. Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM Processors. [Citation Graph (, )][DBLP]


  189. Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Devices. [Citation Graph (, )][DBLP]


  190. Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time Feedback. [Citation Graph (, )][DBLP]


  191. Test Enabled Process Tuning for Adaptive Baseband OFDM Processor. [Citation Graph (, )][DBLP]


  192. ACT: Adaptive Calibration Test for Performance Enhancement and Increased Testability of Wireless RF Front-Ends. [Citation Graph (, )][DBLP]


  193. Fast Accurate Tests for Multi-Carrier Transceiver Specifications: EVM and Noise. [Citation Graph (, )][DBLP]


  194. Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation. [Citation Graph (, )][DBLP]


  195. Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance. [Citation Graph (, )][DBLP]


  196. Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers. [Citation Graph (, )][DBLP]


  197. A DFT Approach for Testing Embedded Systems Using DC Sensors. [Citation Graph (, )][DBLP]


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