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Kurt Keutzer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
    Code density optimization for embedded DSP processors using data compression techniques. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:272-285 [Conf]
  2. Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer
    Programming challenges in network processor deployment. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:178-187 [Conf]
  3. Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer
    An automated exploration framework for FPGA-based soft multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:273-278 [Conf]
  4. Scott J. Weber, Kurt Keutzer
    Using minimal minterms to represent programmability. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:63-68 [Conf]
  5. Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer
    Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:18-23 [Conf]
  6. Raul Camposano, Kurt Keutzer, Jerry Fiddler, Alberto L. Sangiovanni-Vincentelli, Jim Lansford
    HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:76-77 [Conf]
  7. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:80-86 [Conf]
  8. David G. Chinnery, Kurt Keutzer
    Closing the power gap between ASIC and custom: an ASIC perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:275-280 [Conf]
  9. David G. Chinnery, B. Nikolic, Kurt Keutzer
    Achieving 550Mhz in an ASIC Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:420-425 [Conf]
  10. David G. Chinnery, Kurt Keutzer
    Closing the gap between ASIC and custom: an ASIC perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:637-642 [Conf]
  11. Robert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines
    EDA: this is serious business. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:1- [Conf]
  12. Srinivas Devadas, Kurt Keutzer
    Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:221-227 [Conf]
  13. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:359-365 [Conf]
  14. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Certified Timing Verification and the Transition Delay of a Logic Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:549-555 [Conf]
  15. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
    Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:528-533 [Conf]
  16. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
    OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:152-157 [Conf]
  17. Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob White
    Estimation of Average Switching Activity in Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:253-259 [Conf]
  18. Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah
    Is statistical timing statistically significant? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:498- [Conf]
  19. Kurt Keutzer
    DAGON: Technology Binding and Local Optimization by DAG Matching. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:341-347 [Conf]
  20. Kurt Keutzer
    Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:308-313 [Conf]
  21. Kurt Keutzer
    Impact and Evaluation of Competing Implementation Media for ASIC's (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:600- [Conf]
  22. Kurt Keutzer
    What is the Next Big Productivity Boost for Designers? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:141- [Conf]
  23. Kurt Keutzer
    Hardware-Software Co-Design and ESDA. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:435-436 [Conf]
  24. Kurt Keutzer, Sharad Malik, Alexander Saldanha
    Is Redundancy Necessary to Reduce Delay. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:228-234 [Conf]
  25. Kurt Keutzer, Kurt Wolf, David Pietromonaco, Jay Maxey, Jeff Lewis, Martin Lefebvre, Jeff Burns
    Panel: Cell Libraries - Build vs. Buy; Static vs. Dynamic. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:341-342 [Conf]
  26. Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli
    Algorithms for Synthesis of Hazard-Free Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:302-308 [Conf]
  27. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang
    Code Optimization Techniques for Embedded DSP Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:599-604 [Conf]
  28. Michael Orshansky, Kurt Keutzer
    A general probabilistic framework for worst case timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:556-561 [Conf]
  29. Mukul R. Prasad, Philip Chong, Kurt Keutzer
    Why is ATPG Easy? [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:22-28 [Conf]
  30. Patrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh
    A Quick Safari Through the Reconfiguration Jungle. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:172-177 [Conf]
  31. Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
    Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:667-672 [Conf]
  32. Gary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey
    Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:479- [Conf]
  33. Peter Vanbekbergen, Albert Wang, Kurt Keutzer
    A Design and Validation System for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:725-730 [Conf]
  34. Wayne Wolf, Kurt Keutzer, Janaki Akella
    A Kernel-Finding State Assignment Algorithm for Multi-Level Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:433-438 [Conf]
  35. Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert Wang
    Challenges in code generation for embedded processors. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:48-64 [Conf]
  36. Matthias Gries, Chidamber Kulkarni, Christian Sauer, Kurt Keutzer
    Comparing Analytical Modeling with Simulation for Network Processors: A Case Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20256-20261 [Conf]
  37. Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh
    Design Tools for Application Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2002, pp:319-333 [Conf]
  38. Kurt Keutzer
    The Need for Formal Methods for Integrated Circuit Design. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:1-18 [Conf]
  39. Kurt Keutzer
    Challenges in CAD for the One Million Gate FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:133-134 [Conf]
  40. Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer
    Soft multiprocessor systems for network applications (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:271- [Conf]
  41. Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer
    An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:487-492 [Conf]
  42. Michael J. Bryan, Srinivas Devadas, Kurt Keutzer
    Testability-Preserving Circuit Transformations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:456-459 [Conf]
  43. Pinhong Chen, Kurt Keutzer
    Towards true crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:132-138 [Conf]
  44. Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer
    Miller Factor for Gate-Level Coupling Delay Calculation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:68-74 [Conf]
  45. Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer
    Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:331-337 [Conf]
  46. Pinhong Chen, Yuji Kukimoto, Kurt Keutzer
    Refining switching window by time slots for crosstalk noise calculation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:583-586 [Conf]
  47. Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
    An observability-based code coverage metric for functional simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:418-425 [Conf]
  48. Srinivas Devadas, Kurt Keutzer
    An Automata-Theoretic Approach to Behavioral Equivalence. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:30-33 [Conf]
  49. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    Delay Computation in Combinational Logic Circuits: Theory and Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:176-179 [Conf]
  50. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Verification of asynchronous interface circuits with bounded wire delays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:188-195 [Conf]
  51. Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Synthesis for Testability Techniques for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:326-329 [Conf]
  52. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang
    Instruction selection using binate covering for code size optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:393-399 [Conf]
  53. Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
    Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:62-67 [Conf]
  54. Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer
    On average power dissipation and random pattern testability of CMOS combinational logic networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:402-407 [Conf]
  55. Dennis Sylvester, Kurt Keutzer
    Getting to the bottom of deep submicron. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:203-211 [Conf]
  56. Bret M. Victor, Kurt Keutzer
    Bus Encoding to Prevent Crosstalk Delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:57-0 [Conf]
  57. Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik
    Statistical Timing Analysis of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:38-43 [Conf]
  58. Srinivas Devadas, Kurt Keutzer, A. S. Krishnakumar
    Design Verfication and Reachability Analysis Using Algebraic Manipulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:250-258 [Conf]
  59. Masayuki Ito, David G. Chinnery, Kurt Keutzer
    Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:21-0 [Conf]
  60. Kurt Keutzer, Sharad Malik, A. Richard Newton
    From ASIC to ASIP: The Next Design Discontinuity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:84-90 [Conf]
  61. Kurt Keutzer, A. Richard Newton
    The MARCO/DARPA Gigascale Silicon Research Center. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:14-0 [Conf]
  62. Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer
    A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:82-88 [Conf]
  63. David G. Chinnery, Kurt Keutzer
    Linear programming for sizing, Vth and Vdd assignment. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:149-154 [Conf]
  64. Kurt Keutzer, Olivier Coudert, Ramsey W. Haddad
    What is the state of the art in commercial EDA tools for low power? [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:181-187 [Conf]
  65. David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer
    Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:158-163 [Conf]
  66. Pinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer
    On convergence of switching windows computation in presence of crosstalk noise. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:84-89 [Conf]
  67. Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy
    The future of logic synthesis and physical design in deep-submicron process geometries. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:218-224 [Conf]
  68. Dennis Sylvester, Kurt Keutzer
    Getting to the bottom of deep submicron II: a global wiring paradigm. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:193-200 [Conf]
  69. Pinhong Chen, Kurt Keutzer, Desmond Kirkpatrick
    Scripting for EDA Tools: A Case Study. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:87-0 [Conf]
  70. Pranav Ashar, Srinivas Devadas, Kurt Keutzer
    Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:887-896 [Conf]
  71. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:403-410 [Conf]
  72. Srinivas Devadas, Kurt Keutzer
    An algorithmic approach to optimizing fault coverage for BIST logic synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:164-0 [Conf]
  73. Christian Sauer, Matthias Gries, José Ignacio Gómez, Scott J. Weber, Kurt Keutzer
    Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:129-134 [Conf]
  74. Kurt Keutzer, Wayne Wolf
    Anatomy of a Hardware Compiler. [Citation Graph (0, 0)][DBLP]
    PLDI, 1988, pp:95-104 [Conf]
  75. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang
    Storage Assignment to Decrease Code Size. [Citation Graph (0, 0)][DBLP]
    PLDI, 1995, pp:186-195 [Conf]
  76. Kurt Keutzer, Michael Orshansky
    From blind certainty to informed uncertainty. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:37-41 [Conf]
  77. Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer
    Minimum-power retiming for dual-supply CMOS circuits. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:43-49 [Conf]
  78. Kurt Keutzer
    The Need for Formal Verification in Hardware Design and What Formal Verification Has Not Done for Me Lately. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:77-86 [Conf]
  79. Anantha Chandrakasan, Kurt Keutzer, A. Khandekar, S. L. Maskara, B. D. Pradhan, Mani B. Srivastava
    Mobile Communications: Demands on VLSI Technology, Design and CAD. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:432-436 [Conf]
  80. Kurt Keutzer, Sharad Malik
    Register Transfer Level Synthesis: From Theory to Practice. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:2- [Conf]
  81. Dennis Sylvester, Kurt Keutzer
    Rethinking Deep-Submicron Circuit Design. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:11, pp:25-33 [Journal]
  82. Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik
    Developing Architectural Platforms: A Disciplined Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:6-16 [Journal]
  83. Serdar Tasiran, Kurt Keutzer
    Coverage Metrics for Functional Validation of Hardware Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:36-45 [Journal]
  84. Pranav Ashar, Srinivas Devadas, Kurt Keutzer
    Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1993, v:2, n:1, pp:93-112 [Journal]
  85. Niraj Shah, William Plishker, Kaushik Ravindran, Kurt Keutzer
    NP-Click: A Productive Software Development Approach for Network Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:5, pp:45-54 [Journal]
  86. Michael J. Bryan, Srinivas Devadas, Kurt Keutzer
    Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:800-803 [Journal]
  87. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    Delay-fault test generation and synthesis for testability under a standard scan design methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1217-1231 [Journal]
  88. Srinivas Devadas, Kurt Keutzer
    A unified approach to the synthesis of fully testable sequential machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:39-50 [Journal]
  89. Srinivas Devadas, Kurt Keutzer
    Synthesis of robust delay-fault-testable circuits: theory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:87-101 [Journal]
  90. Srinivas Devadas, Kurt Keutzer
    Synthesis of robust delay-fault-testable circuits: practice. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:277-300 [Journal]
  91. Srinivas Devadas, Kurt Keutzer
    Validatable nonrobust delay-fault testable circuits via logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1559-1573 [Journal]
  92. Srinivas Devadas, Kurt Keutzer
    Addendum to "Synthesis of robust delay-fault testable circuits: Theory". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:4, pp:445-446 [Journal]
  93. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    Computation of floating mode delay in combinational circuits: theory and algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1913-1923 [Journal]
  94. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Computation of floating mode delay in combinational circuits: practice and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1924-1936 [Journal]
  95. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:814-822 [Journal]
  96. Srinivas Devadas, Kurt Keutzer, Jacob K. White
    Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:373-383 [Journal]
  97. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
    Functional vector generation for HDL models using linearprogramming and Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:994-1002 [Journal]
  98. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
    OCCOM-efficient computation of observability-based code coveragemetrics for functional verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:1003-1015 [Journal]
  99. Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison
    On properties of algebraic transformations and the synthesis of multifault-irredundant circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:313-321 [Journal]
  100. Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Synthesis for testability techniques for asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1569-1577 [Journal]
  101. Kurt Keutzer, Sharad Malik, Alexander Saldanha
    Is redundancy necessary to reduce delay? [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:427-435 [Journal]
  102. Kurt Keutzer, A. Richard Newton, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
    System-level design: orthogonalization of concerns andplatform-based design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1523-1543 [Journal]
  103. Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli
    Synthesis of hazard-free asynchronous circuits with bounded wire delays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:61-86 [Journal]
  104. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
    Code density optimization for embedded DSP processors using data compression techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:601-608 [Journal]
  105. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White
    Estimation of average switching activity in combinational logic circuits using symbolic simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:121-127 [Journal]
  106. Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
    Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:544-553 [Journal]
  107. Dennis Sylvester, Kurt Keutzer
    A global wiring paradigm for deep submicron design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:242-252 [Journal]
  108. Wayne Wolf, Kurt Keutzer, Janaki Akella
    Addendum to 'A kernel-finding state assignment algorithm for multi-level logic'. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:925-927 [Journal]
  109. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
    A text-compression-based method for code size minimization in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:1, pp:12-38 [Journal]
  110. Stan Y. Liao, Kurt Keutzer, Steven W. K. Tjiang, Srinivas Devadas
    A new viewpoint on code generation for directed acyclic graphs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:1, pp:51-75 [Journal]
  111. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang
    Storage Assignment to Decrease Code Size. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1996, v:18, n:3, pp:235-253 [Journal]
  112. Francine Bacchini, Greg Spirakis, Juan Antonio Carballo, Kurt Keutzer, Aart J. de Geus, Fu-Chieh Hsu, Kazu Yamada
    Megatrends and EDA 2017. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:21-22 [Conf]
  113. Nadathur Satish, Kaushik Ravindran, Kurt Keutzer
    A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:57-62 [Conf]
  114. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Certified timing verification and the transition delay of a logic circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:333-342 [Journal]

  115. Reinventing EDA with manycore processors. [Citation Graph (, )][DBLP]


  116. Parallelizing CAD: a timely research agenda for EDA. [Citation Graph (, )][DBLP]


  117. Scheduling task dependence graphs with variable task execution times onto heterogeneous multiprocessors. [Citation Graph (, )][DBLP]


  118. Optimizing the use of GPU memory in applications with large data sets. [Citation Graph (, )][DBLP]


  119. Architecting parallel programs. [Citation Graph (, )][DBLP]


  120. Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling. [Citation Graph (, )][DBLP]


  121. Scalable HMM based inference engine in large vocabulary continuous speech recognition. [Citation Graph (, )][DBLP]


  122. Fast support vector machine training and classification on graphics processors. [Citation Graph (, )][DBLP]


  123. Acceleration of market value-at-risk estimation. [Citation Graph (, )][DBLP]


  124. Image feature extraction for mobile processors. [Citation Graph (, )][DBLP]


  125. A view of the parallel computing landscape. [Citation Graph (, )][DBLP]


  126. The Concurrency Challenge. [Citation Graph (, )][DBLP]


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