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Trevor N. Mudge: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Timothy J. Stanley, Trevor N. Mudge
    Systematic objective-driven computer architecture optimization. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:286-303 [Conf]
  2. Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge
    Opportunities and challenges for better than worst-case design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:2-7 [Conf]
  3. Krisztián Flautner, Richard Uhlig, Steven K. Reinhardt, Trevor N. Mudge
    Thread Level Parallelism and Interactive Performance of Desktop Applications. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:129-138 [Conf]
  4. Bruce L. Jacob, Trevor N. Mudge
    A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:295-306 [Conf]
  5. I-Cheng K. Chen, John T. Coffey, Trevor N. Mudge
    Analysis of Branch Prediction Via Data Compression. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1996, pp:128-137 [Conf]
  6. Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest
    Trap-driven Simulation with Tapeworm II. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:132-144 [Conf]
  7. Michael Upton, Thomas Huff, Trevor N. Mudge, Richard B. Brown
    Resource Allocation in a High Clock Rate Microprocessor. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:98-109 [Conf]
  8. Taeho Kgil, Shaun D'Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Trevor N. Mudge, Steven K. Reinhardt, Krisztián Flautner
    PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:117-128 [Conf]
  9. Hyunseok Lee, Trevor N. Mudge
    A dual-processor solution for the MAC layer of a software defined radio terminal. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:257-265 [Conf]
  10. Taeho Kgil, Trevor N. Mudge
    FlashCache: a NAND flash memory file cache for low power web servers. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:103-112 [Conf]
  11. Ronald G. Dreslinski, Ali G. Saidi, Trevor N. Mudge, Steven K. Reinhardt
    Analysis of hardware prefetching across virtual page boundaries. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:13-22 [Conf]
  12. Trevor N. Mudge
    Performance and power analysis of computer systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:2- [Conf]
  13. Janos Sztipanovits, C. John Glossner, Trevor N. Mudge, Chris Rowen, Alberto L. Sangiovanni-Vincentelli, Wayne Wolf, Feng Zhao
    Grand challenges in embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:333- [Conf]
  14. David Van Campenhout, Trevor N. Mudge, John P. Hayes
    High-Level Test Generation for Design Verification of Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:185-188 [Conf]
  15. Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge
    FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:920-923 [Conf]
  16. Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge
    Reliability modeling and management in dynamic microprocessor-based systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1057-1060 [Conf]
  17. Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge
    Circuit-aware architectural simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:305-310 [Conf]
  18. Kunle Olukotun, Trevor N. Mudge
    A Preliminary Investigation into Parallel Routing on a Hypercube Computer. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:814-820 [Conf]
  19. Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun
    Analysis and Design of Latch-Controlled Synchronous Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:111-117 [Conf]
  20. Richard Uhlig, Trevor N. Mudge
    Trace-Driven Memory Simulation: A Survey. [Citation Graph (0, 0)][DBLP]
    Performance Evaluation, 2000, pp:97-139 [Conf]
  21. Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge
    Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:650-651 [Conf]
  22. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:80-85 [Conf]
  23. Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge
    Total leakage optimization strategies for multi-level caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:381-384 [Conf]
  24. Trevor N. Mudge
    Power: A First Class Design Constraint for Future Architecture and Automation. [Citation Graph (0, 0)][DBLP]
    HiPC, 2000, pp:215-224 [Conf]
  25. Trevor N. Mudge
    Low Power Robust Computing. [Citation Graph (0, 0)][DBLP]
    HiPC, 2004, pp:6- [Conf]
  26. Hyunseok Lee, Yuan Lin, Yoav Harel, Mark Woh, Scott A. Mahlke, Trevor N. Mudge, Krisztián Flautner
    Software Defined Radio - A High Performance Embedded Challenge. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:6-26 [Conf]
  27. Bruce L. Jacob, Trevor N. Mudge
    Software-Managed Address Translation. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:156-167 [Conf]
  28. Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
    Reducing Code Size with Run-Time Decompression. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:218-0 [Conf]
  29. Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh
    An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICAC, 2005, pp:263-273 [Conf]
  30. Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge
    Identification of critical paths in circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:137-141 [Conf]
  31. David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah
    Timing verification of sequential domino circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:127-132 [Conf]
  32. Nam Sung Kim, David Blaauw, Trevor N. Mudge
    Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:627-632 [Conf]
  33. Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David Blaauw
    Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:721-725 [Conf]
  34. Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun
    check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:552-555 [Conf]
  35. Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge
    Total power-optimal pipelining and parallel processing under process variations in nanometer technology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:535-540 [Conf]
  36. I-Cheng K. Chen, Chih-Chieh Lee, Trevor N. Mudge
    Instruction Prefetching Using Branch Prediction Information. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:593-601 [Conf]
  37. I-Cheng K. Chen, Chih-Chieh Lee, Matt Postiff, Trevor N. Mudge
    Design Optimization for High-speed Per-address Two-level Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:88-96 [Conf]
  38. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
    Optimal Clocking of Circular Pipelines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:642-650 [Conf]
  39. Trevor N. Mudge, B. A. Makrucki
    An Approximate Queueing Model for Packet Switched Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1982, pp:556-562 [Conf]
  40. Timothy J. Stanley, Trevor N. Mudge
    A Parallel Genetic Algorithm for Multiobjective Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    ICGA, 1995, pp:597-604 [Conf]
  41. John P. Hayes, Trevor N. Mudge, Quentin F. Stout
    Architecture of a Hypercube Supercomputer. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:653-660 [Conf]
  42. Trevor N. Mudge, Humoud B. Al-Sadoun
    A Semi-Markov Model for the Performance of Multiple-Bus Systems. [Citation Graph (0, 0)][DBLP]
    ICPP, 1985, pp:521-530 [Conf]
  43. Trevor N. Mudge, Abdel-Rahman H. Tawil
    Efficiency of Feature Dependent Algorithms for the Parallel Processing of Images. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:369-373 [Conf]
  44. Donald C. Winsor, Trevor N. Mudge
    Crosspoint Cache Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:266-269 [Conf]
  45. James Dundas, Trevor N. Mudge
    Improving Data Cache Performance by Pre-Executing Instructions Under a Cache Miss. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:68-75 [Conf]
  46. Nam Sung Kim, Trevor N. Mudge
    Reducing register ports using delayed write-back queues and operand pre-fetch. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:172-182 [Conf]
  47. Matt Postiff, David Greene, Steven Raasch, Trevor N. Mudge
    Integrating superscalar processor components to implement register caching. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:348-357 [Conf]
  48. Jim Pierce, Trevor N. Mudge
    The Effect of Speculative Execution on Cache Performance. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:172-179 [Conf]
  49. Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge
    A Performance Comparison of Contemporary DRAM Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:222-233 [Conf]
  50. Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor N. Mudge
    Drowsy Caches: Simple Techniques for Reducing Leakage Power. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:148-157 [Conf]
  51. Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    SODA: A Low-power Architecture For Software Radio. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:89-101 [Conf]
  52. Kunle Olukotun, Trevor N. Mudge, Richard B. Brown
    Implementing a Cache for a High-Performance GaAs Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:138-147 [Conf]
  53. Kunle Olukotun, Trevor N. Mudge, Richard B. Brown
    Performance Optimization of Pipelined Primary Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:181-190 [Conf]
  54. Trevor N. Mudge, B. A. Makrucki
    Probabilistic analysis of a crossbar switch. [Citation Graph (0, 0)][DBLP]
    ISCA, 1982, pp:311-320 [Conf]
  55. David Nagle, Richard Uhlig, Trevor N. Mudge, Stuart Sechrest
    Optimal Allocation of On-Chip Memory for Multiple-API Operating Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:358-369 [Conf]
  56. David Nagle, Richard Uhlig, Tim Stanley, Stuart Sechrest, Trevor N. Mudge, Richard B. Brown
    Design Tradeoffs for Software-Managed TLBs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:27-38 [Conf]
  57. Stuart Sechrest, Chih-Chieh Lee, Trevor N. Mudge
    Correlation and Aliasing in Dynamic Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:22-32 [Conf]
  58. Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer
    Instruction Fetching: Coping with Code Bloat. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:345-356 [Conf]
  59. Donald C. Winsor, Trevor N. Mudge
    Analysis of Bus Hierarchies for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:100-107 [Conf]
  60. Brian Davis, Bruce L. Jacob, Trevor N. Mudge
    The New DRAM Interfaces: SDRAM, RDRAM and Variants. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:26-31 [Conf]
  61. Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge
    Reducing pipeline energy demands with local DVS and dynamic retiming. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:319-324 [Conf]
  62. Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge
    Microarchitectural power modeling techniques for deep sub-micron microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:212-217 [Conf]
  63. Nam Sung Kim, Trevor N. Mudge
    The microarchitecture of a low power register file. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:384-389 [Conf]
  64. Hyunseok Lee, Trevor N. Mudge, Chaitali Chakrabarti
    Reducing idle mode power in software defined radio terminals. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:101-106 [Conf]
  65. David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner
    Error Analysis for the Support of Robust Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:65-70 [Conf]
  66. Jim Pierce, Trevor N. Mudge
    IDtrace - A Tracing Tool for i486 Simulation. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1994, pp:419-420 [Conf]
  67. A. N. Eden, Trevor N. Mudge
    The YAGS Branch Prediction Scheme. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:69-77 [Conf]
  68. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge
    Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:7-18 [Conf]
  69. Michael Golden, Trevor N. Mudge
    A comparison of two pipeline organizations. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:153-161 [Conf]
  70. Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge
    Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:219-230 [Conf]
  71. Chih-Chieh Lee, I-Cheng K. Chen, Trevor N. Mudge
    The bi-Mode Branch Predictor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:4-13 [Conf]
  72. Charles Lefurgy, Peter L. Bird, I-Cheng K. Chen, Trevor N. Mudge
    Improving Code Density Using Compression Techniques. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:194-203 [Conf]
  73. Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
    Evaluation of a High Performance Code Compression Method. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:93-102 [Conf]
  74. David W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt
    How to Fake 1000 Registers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:7-18 [Conf]
  75. Jim Pierce, Trevor N. Mudge
    Wrong-path Instruction Prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:165-175 [Conf]
  76. Matt Postiff, David Greene, Trevor N. Mudge
    The store-load address table and speculative register promotion. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:235-244 [Conf]
  77. Stuart Sechrest, Chih-Chieh Lee, Trevor N. Mudge
    The role of adaptivity in two-level adaptive branch prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:264-269 [Conf]
  78. Tim Stanley, Michael Upton, Patrick Sherhart, Trevor N. Mudge, Richard B. Brown
    A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:31-40 [Conf]
  79. Krisztián Flautner, Steven K. Reinhardt, Trevor N. Mudge
    Automatic performance setting for dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    MOBICOM, 2001, pp:260-271 [Conf]
  80. Krisztián Flautner, Trevor N. Mudge
    Vertigo: Automatic Performance-Setting for Linux. [Citation Graph (0, 0)][DBLP]
    OSDI, 2002, pp:- [Conf]
  81. Richard A. Volz, Trevor N. Mudge
    Instruction Level Mechanisms for Accurate Real-time Task Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1986, pp:209-215 [Conf]
  82. Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest
    Kernel-Based Memory Simulation. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1994, pp:286-287 [Conf]
  83. Bruce L. Jacob, Trevor N. Mudge
    The trading function in action. [Citation Graph (0, 0)][DBLP]
    ACM SIGOPS European Workshop, 1996, pp:241-247 [Conf]
  84. Russell M. Clapp, Louis Duchesneau, Richard A. Volz, Trevor N. Mudge, Timothy Schultze
    Toward Real-Time Performance Benchmarks for Ada. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1986, v:29, n:8, pp:760-778 [Journal]
  85. Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner
    Making Typical Silicon Matter with Razor. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:3, pp:57-65 [Journal]
  86. Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf
    Mobile Supercomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:5, pp:81-83 [Journal]
  87. Gregory D. Buzzard, Trevor N. Mudge
    Object-Based Computing and the Ada Programming Language. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1985, v:18, n:3, pp:11-19 [Journal]
  88. Bruce L. Jacob, Trevor N. Mudge
    Virtual Memory: Issues of Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:6, pp:33-43 [Journal]
  89. Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan
    Leakage Current: Moore's Law Meets Static Power. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:68-75 [Journal]
  90. Trevor N. Mudge
    Power: A First-Class Architectural Design Constraint. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:4, pp:52-58 [Journal]
  91. Trevor N. Mudge, Richard B. Brown, William P. Bimingham, Jeffrey A. Dykstra, Ayman I. Kayssi, Ronald J. Lomax, Kunle Olukotun, Karem A. Sakallah, Raymond A. Milano
    The Design of a Microsupercomputer. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:57-64 [Journal]
  92. Trevor N. Mudge
    Strategic Directions in Computer Architecture. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:4, pp:671-678 [Journal]
  93. Richard Uhlig, Trevor N. Mudge
    Trace-Driven Memory Simulation: A Survey. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1997, v:29, n:2, pp:128-170 [Journal]
  94. David Van Campenhout, Trevor N. Mudge, John P. Hayes
    Collection and Analysis of Microprocessor Design Errors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:51-60 [Journal]
  95. Paul G. Gottschalk, Jerry L. Turney, Trevor N. Mudge
    Efficient Recognition of Partially Visible Objects Using a Logarithmic Complexity Matching Technique. [Citation Graph (0, 0)][DBLP]
    I. J. Robotic Res., 1989, v:8, n:6, pp:110-131 [Journal]
  96. David Blaauw, Steve Martin, Trevor N. Mudge, Krisztián Flautner
    Leakage Current Reduction in VLSI Systems. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:6, pp:621-636 [Journal]
  97. Matt Postiff, Gary S. Tyson, Trevor N. Mudge
    Performance Limits of Trace Caches. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 1999, v:1, n:, pp:- [Journal]
  98. Oyekunle A. Olukotun, Trevor N. Mudge
    Hierarchical Gate-Array Routing on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1990, v:8, n:4, pp:313-324 [Journal]
  99. Trevor N. Mudge, T. S. Abdel-Rahman
    Vision Algorithms for Hypercube Machines. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1987, v:4, n:1, pp:79-94 [Journal]
  100. Trevor N. Mudge, John P. Hayes, Gregory D. Buzzard, Donald C. Winsor
    Analysis of Multiple-Bus Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1986, v:3, n:3, pp:328-343 [Journal]
  101. Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner
    Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:10-20 [Journal]
  102. Taeho Kgil, Laura Falk, Trevor N. Mudge
    ChipLock: support for secure microarchitectures. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:134-143 [Journal]
  103. Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge
    High-Performance DRAMs in Workstation Environments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1133-1153 [Journal]
  104. Bruce L. Jacob, Peter M. Chen, Seth R. Silverman, Trevor N. Mudge
    An Analytical Model for Designing Memory Hierarchies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:10, pp:1180-1194 [Journal]
  105. Bruce L. Jacob, Peter M. Chen, Seth R. Silverman, Trevor N. Mudge
    A Comment on ``An Analytical Model for Designing Memory Hierarchies''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:10, pp:1151- [Journal]
  106. Bruce L. Jacob, Trevor N. Mudge
    Uniprocessor Virtual Memory without TLBs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:5, pp:482-499 [Journal]
  107. Trevor N. Mudge
    Introduction to the Special Section on Energy Efficient Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:641-0 [Journal]
  108. Trevor N. Mudge, Humoud B. Al-Sadoun
    Memory Interference Models with Variable Connection Time. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:11, pp:1033-1038 [Journal]
  109. Trevor N. Mudge, Humoud B. Al-Sadoun
    A Semi-Markov Model for the Performance of Multiple-Bus Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:10, pp:934-942 [Journal]
  110. Kunle Olukotun, Trevor N. Mudge, Richard B. Brown
    Multilevel Optimization of Pipelined Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:10, pp:1083-1102 [Journal]
  111. Richard A. Volz, Trevor N. Mudge
    Timing Issues in the Distributed Execution of Ada Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:4, pp:449-459 [Journal]
  112. Richard A. Volz, Trevor N. Mudge
    Instruction Level Timing Mechanisms for Accurate Real-Time Task Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:8, pp:988-993 [Journal]
  113. David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah
    Timing verification of sequential dynamic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:645-658 [Journal]
  114. Rob A. Rutenbar, Trevor N. Mudge, Daniel E. Atkins
    A Class of Cellular Architectures to Support Physical Design Automation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:4, pp:264-278 [Journal]
  115. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
    Synchronization of pipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1132-1146 [Journal]
  116. Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun
    Analysis and design of latch-controlled synchronous digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:322-333 [Journal]
  117. Guang R. Gao, Trevor N. Mudge
    Special issue on compilers, architecture, and synthesis for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:2, pp:131- [Journal]
  118. Ahmed Amine Jerraya, Trevor N. Mudge
    Guest editorial: Concurrent hardware and software design for multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:259-262 [Journal]
  119. Richard Uhlig, David Nagle, Tim Stanley, Trevor N. Mudge, Stuart Sechrest, Richard B. Brown
    Design Tradeoffs for Software-Managed TLBs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1994, v:12, n:3, pp:175-205 [Journal]
  120. David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown
    High-level design verification of microprocessors via error modeling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:581-599 [Journal]
  121. Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest
    Trap-Driven Memory Simulation with Tapeworm II. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Model. Comput. Simul., 1997, v:7, n:1, pp:7-41 [Journal]
  122. Richard A. Volz, Trevor N. Mudge, Gregory D. Buzzard, Padmanabhan Krishnan
    Translation and Execution of Distributed Ada Programs: Is It Still Ada? [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1989, v:15, n:3, pp:281-292 [Journal]
  123. Nam Sung Kim, David Blaauw, Trevor N. Mudge
    Quantitative analysis and optimization techniques for on-chip cache leakage power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1147-1156 [Journal]
  124. Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge
    Circuit and microarchitectural techniques for reducing cache leakage power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:167-184 [Journal]
  125. Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevor N. Mudge
    Hierarchical coarse-grained stream compilation for software defined radio. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:115-124 [Conf]
  126. Trevor N. Mudge
    Multicore architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:208- [Conf]
  127. Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    The Next Generation Challenge for Software Defined Radio. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:343-354 [Conf]
  128. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  129. Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge
    Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  130. Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    SODA: A High-Performance DSP Architecture for Software-Defined Radio. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:114-123 [Journal]
  131. Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge
    Critical paths in circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:273-291 [Journal]
  132. Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge
    Overview of complementary GaAs technology for high-speed VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:47-51 [Journal]

  133. An Energy Efficient Parallel Architecture Using Near Threshold Operation. [Citation Graph (, )][DBLP]


  134. Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures. [Citation Graph (, )][DBLP]


  135. MacroSS: macro-SIMDization of streaming applications. [Citation Graph (, )][DBLP]


  136. Stream Compilation for Real-Time Embedded Multicore Systems. [Citation Graph (, )][DBLP]


  137. Using non-volatile memory to save energy in servers. [Citation Graph (, )][DBLP]


  138. On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology. [Citation Graph (, )][DBLP]


  139. Yield-driven near-threshold SRAM design. [Citation Graph (, )][DBLP]


  140. Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments. [Citation Graph (, )][DBLP]


  141. Improving NAND Flash Based Disk Caches. [Citation Graph (, )][DBLP]


  142. Disaggregated memory for expansion and sharing in blade servers. [Citation Graph (, )][DBLP]


  143. AnySP: anytime anywhere anyway signal processing. [Citation Graph (, )][DBLP]


  144. End-to-end performance forecasting: finding bottlenecks before they happen. [Citation Graph (, )][DBLP]


  145. Evolution of thread-level parallelism in desktop applications. [Citation Graph (, )][DBLP]


  146. Energy efficient near-threshold chip multi-processing. [Citation Graph (, )][DBLP]


  147. Diet SODA: a power-efficient processor for digital cameras. [Citation Graph (, )][DBLP]


  148. PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis. [Citation Graph (, )][DBLP]


  149. Full-System Critical Path Analysis. [Citation Graph (, )][DBLP]


  150. Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification. [Citation Graph (, )][DBLP]


  151. SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code. [Citation Graph (, )][DBLP]


  152. Proactive transaction scheduling for contention management. [Citation Graph (, )][DBLP]


  153. From SODA to scotch: The evolution of a wireless baseband processor. [Citation Graph (, )][DBLP]


  154. Reconfigurable energy efficient near threshold cache architectures. [Citation Graph (, )][DBLP]


  155. Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. [Citation Graph (, )][DBLP]


  156. Reconfigurable Multicore Server Processors for Low Power Operation. [Citation Graph (, )][DBLP]


  157. A parameterized dataflow language extension for embedded streaming systems. [Citation Graph (, )][DBLP]


  158. PicoServer - building a compact energy efficient multiprocessor. [Citation Graph (, )][DBLP]


  159. Customizing wide-SIMD architectures for H.264. [Citation Graph (, )][DBLP]


  160. Design and Analysis of LDPC Decoders for Software Defined Radio. [Citation Graph (, )][DBLP]


  161. Design and Implementation of Turbo Decoders for Software Defined Radio. [Citation Graph (, )][DBLP]


  162. Analyzing the scalability of SIMD for the next generation software defined radio. [Citation Graph (, )][DBLP]


  163. Integrating NAND flash devices onto servers. [Citation Graph (, )][DBLP]


  164. Mobile Supercomputers for the Next-Generation Cell Phone. [Citation Graph (, )][DBLP]


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