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Rajit Manohar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rajit Manohar
    Width-Adaptive Data Word Architectures. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:112-131 [Conf]
  2. Rajit Manohar, Mika Nyström, Alain J. Martin
    Precise Exceptions in Asynchronous Processors. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:16-28 [Conf]
  3. Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings
    The Design of an Asynchronous MIPS R3000 Microprocessor. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:164-181 [Conf]
  4. Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar
    An ultra low-power processor for sensor networks. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:27-36 [Conf]
  5. Virantha N. Ekanayake, Rajit Manohar
    Asynchronous DRAM Design and Synthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:174-183 [Conf]
  6. Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar
    BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2005, pp:144-154 [Conf]
  7. David Fang, Rajit Manohar
    Non-Uniform Access Asynchronous Register Files. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:75-85 [Conf]
  8. Clinton Kelly IV, Virantha N. Ekanayake, Rajit Manohar
    SNAP: A Sensor-Network Asynchronous Processor. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:24-35 [Conf]
  9. John Teifel, Rajit Manohar
    A High-Speed Clockless Serial Link Transceiver. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:151-163 [Conf]
  10. John Teifel, Rajit Manohar
    Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:17-27 [Conf]
  11. Rajit Manohar
    An Analysis of Reshuffled Handshaking Expansions. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:96-0 [Conf]
  12. Rajit Manohar, Clinton Kelly IV, John Teifel, David Fang, David Biermann
    Energy-Efficient Pipelines. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:23-0 [Conf]
  13. Rajit Manohar, Tak-Kwan Lee, Alain J. Martin
    Projection: A Synthesis Technique for Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:125-134 [Conf]
  14. Song Peng, Rajit Manohar
    Self-Healing Asynchronous Arrays. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:34-45 [Conf]
  15. Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel
    A Level-Crossing Flash Asynchronous Analog-to-Digital Converter. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:12-22 [Conf]
  16. Song Peng, Rajit Manohar
    Efficient Failure Detection in Pipelined Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:484-493 [Conf]
  17. Christopher LaFrieda, Rajit Manohar
    Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:41-50 [Conf]
  18. Clinton Kelly IV, Rajit Manohar
    An Event-Synchronization Protocol for Parallel Simulation of Large-Scale Wireless Networks. [Citation Graph (0, 0)][DBLP]
    DS-RT, 2003, pp:110-119 [Conf]
  19. David Fang, John Teifel, Rajit Manohar
    A High-Performance Asynchronous FPGA: Test Results. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:271-272 [Conf]
  20. Song Peng, David Fang, John Teifel, Rajit Manohar
    Automated synthesis for asynchronous FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:163-173 [Conf]
  21. John Teifel, Rajit Manohar
    Highly pipelined asynchronous FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:133-142 [Conf]
  22. John Teifel, Rajit Manohar
    Programmable Asynchronous Pipeline Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:345-354 [Conf]
  23. Song Peng, Rajit Manohar
    Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:159-164 [Conf]
  24. Song Peng, Rajit Manohar
    Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:171-179 [Conf]
  25. K. Mani Chandy, Rajit Manohar, Berna L. Massingill, Daniel I. Meiron
    Integrating task and data parallelism with the group communication archetype. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:724-733 [Conf]
  26. Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari
    Mapping system-on-chip designs from 2-D to 3-D ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2939-2942 [Conf]
  27. David Fang, Filipp Akopyan, Rajit Manohar
    Self-Timed Thermally-Aware Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:438-439 [Conf]
  28. Rajit Manohar, Alain J. Martin
    Slack Elasticity in Concurrent Computing. [Citation Graph (0, 0)][DBLP]
    MPC, 1998, pp:272-285 [Conf]
  29. Rajit Manohar
    Scalable formal design methods for asynchronous VLSI. [Citation Graph (0, 0)][DBLP]
    POPL, 2002, pp:245-246 [Conf]
  30. Rajit Manohar, K. Rustan M. Leino
    Conditional Composition. [Citation Graph (0, 0)][DBLP]
    Formal Asp. Comput., 1995, v:7, n:6, pp:683-703 [Journal]
  31. Donald Dabdub, Rajit Manohar
    Performance and Portability of an Air Quality Model. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1997, v:23, n:14, pp:2187-2200 [Journal]
  32. Rajit Manohar, José A. Tierno
    Asynchronous Parallel Prefix Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:11, pp:1244-1252 [Journal]
  33. John Teifel, Rajit Manohar
    An Asynchronous Dataflow FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1376-1392 [Journal]
  34. K. Rustan M. Leino, Rajit Manohar
    Joining Specification Statements. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1999, v:216, n:1-2, pp:375-394 [Journal]
  35. Rajit Manohar
    The entropy of traces in parallel computation. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Theory, 1999, v:45, n:5, pp:1606-1608 [Journal]
  36. Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar
    Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:317-326 [Conf]

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