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James D. Meindl: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl
    Exploring Microprocessor Architectures for Gigascale Integration. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:242-255 [Conf]
  2. James D. Meindl
    XXI Century Gigascale Integration (GSI) : The Interconnect Problem. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:88-0 [Conf]
  3. Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl
    A physical model for the transient response of capacitively loaded distributed rlc interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:763-766 [Conf]
  4. Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl
    CMOS system-on-a-chip voltage scaling beyond 50nm. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:7-12 [Conf]
  5. Kaveh Shakeri, James D. Meindl
    A compact delay model for series-connected MOSFETs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:37-40 [Conf]
  6. Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
    Interconnect-centric Array Architectures for Minimum SRAM Access Time. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:400-405 [Conf]
  7. James D. Meindl
    Design and Test Automation-Gigascale Integration (GSI) in the 21st Century. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:438- [Conf]
  8. Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl
    On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:214-220 [Conf]
  9. R. Murali, Lihui Wang, Blanca Austin, James D. Meindl
    Low-power circuit advantages of the scaled accumulation FET. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:201-204 [Conf]
  10. Vivek De, James D. Meindl
    A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:371-375 [Conf]
  11. Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl
    Minimum supply voltage for bulk Si CMOS GSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:100-102 [Conf]
  12. Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
    Circuit techniques for low-power CMOS GSI. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:193-196 [Conf]
  13. James D. Meindl
    A history of low power electronics: how it began and where it's headed. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:149-151 [Conf]
  14. Xinghai Tang, Vivek De, James D. Meindl
    Effects of random MOSFET parameter fluctuations on total power consumption. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:233-236 [Conf]
  15. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
    Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:167-172 [Conf]
  16. Kaveh Shakeri, James D. Meindl
    Temperature Variable Supply Voltage for Power Reduction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:71-74 [Conf]
  17. James D. Meindl
    Gigascale integration (GSI) technology. [Citation Graph (0, 0)][DBLP]
    SC, 1991, pp:534-538 [Conf]
  18. Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
    Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:147-148 [Conf]
  19. Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
    Prediction of interconnect fan-out distribution using Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:107-112 [Conf]
  20. James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:123-127 [Conf]
  21. James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl
    Interconnect opportunities for gigascale integration. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:245-264 [Journal]
  22. James D. Meindl
    Interconnect Opportunities for Gigascale Integration. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:3, pp:28-35 [Journal]
  23. Lucian Codrescu, D. Scott Wills, James D. Meindl
    Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:1, pp:67-82 [Journal]
  24. James W. Joyner, Payman Zarkesh-Ha, James D. Meindl
    Global interconnect design in a three-dimensional system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:367-372 [Journal]
  25. Azad Naeemi, Reza Sarvari, James D. Meindl
    Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:568-573 [Conf]
  26. Azad Naeemi, James D. Meindl
    Carbon nanotube interconnects. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:77-84 [Conf]
  27. Xinghai Tang, Vivek De, James D. Meindl
    Intrinsic MOSFET parameter fluctuations due to random dopant placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:369-376 [Journal]
  28. Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl
    Heterogeneous architecture models for interconnect-motivated system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:660-670 [Journal]
  29. Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl
    A compact physical via blockage model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:689-692 [Journal]
  30. Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl
    A minimum total power methodology for projecting limits on CMOS GSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:235-251 [Journal]
  31. Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:649-659 [Journal]
  32. James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Impact of three-dimensional architectures on interconnects in gigascale integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:922-928 [Journal]
  33. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
    Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:899-912 [Journal]
  34. A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl
    Electrical and optical clock distribution networks for gigascale microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:582-594 [Journal]
  35. Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills
    Modeling technology impact on cluster microprocessor performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:909-920 [Journal]

  36. IntSim: A CAD tool for optimization of multilevel interconnect networks. [Citation Graph (, )][DBLP]


  37. Physical models for electron transport in graphene nanoribbons and their junctions. [Citation Graph (, )][DBLP]


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