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Carl Ebeling: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Darren C. Cronquist, Chris Fisher, Miguel Figueroa, Paul Franklin, Carl Ebeling
    Architecture Design of Reconfigurable Pipelined Datapaths. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:23-41 [Conf]
  2. Carl Ebeling, Brian Lockyear
    On the performance of level-clocked circuits. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:342-357 [Conf]
  3. Carl Ebeling
    Configurable Computing Platforms - Promises, Promises. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:3-4 [Conf]
  4. Carl Ebeling, Darren C. Cronquist, Paul Franklin
    Configurable computing: the catalyst for high-performance architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:364-373 [Conf]
  5. Soha Hassoun, Carl Ebeling
    Architectural Retiming: Pipelining Latency-Constrained Circuts. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:708-713 [Conf]
  6. Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather
    SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:31-37 [Conf]
  7. Darren C. Cronquist, Paul Franklin, Stefan G. Berg, Carl Ebeling
    Specifying and Compiling Applications for RaPiD. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:116-125 [Conf]
  8. Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg
    Mapping applications to the RaPiD configurable architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:106-115 [Conf]
  9. Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
    A Type Architecture for Hybrid Micro-Parallel Computers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:99-110 [Conf]
  10. John F. Keane, Christopher Bradley, Carl Ebeling
    A compiled accelerator for biological cell signaling simulations. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:233-241 [Conf]
  11. Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling
    MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:44-51 [Conf]
  12. Larry McMurchie, Carl Ebeling
    PathFinder: A Negotiation-based Performance-driven Router for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:111-117 [Conf]
  13. Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck
    Exploration of pipelined FPGA interconnect structures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:13-22 [Conf]
  14. Akshay Sharma, Carl Ebeling, Scott Hauck
    PipeRoute: a pipelining-aware router for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:68-77 [Conf]
  15. Akshay Sharma, Carl Ebeling, Scott Hauck
    Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:266- [Conf]
  16. Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
    A type architecture for hybrid micro-parallel computers. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:227- [Conf]
  17. Carl Ebeling, Darren C. Cronquist, Paul Franklin
    RaPiD - Reconfigurable Pipelined Datapath. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:126-135 [Conf]
  18. Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu
    Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:21-30 [Conf]
  19. Chris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John H. Naegle, Daniel Parshall, Dmitriy Portnov, Adnan Sulejmanpasic, Carl Ebeling
    An Emulator for Exploring RaPiD Configurable Computing Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:17-26 [Conf]
  20. Akshay Sharma, Carl Ebeling, Scott Hauck
    Architecture-Adaptive Routability-Driven Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:427-432 [Conf]
  21. Carl Ebeling
    Whither Configurable Computing? [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1997, pp:713- [Conf]
  22. Soha Hassoun, Carl Ebeling
    Using precomputation in architecture and logic resynthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:316-323 [Conf]
  23. Brian Lockyear, Carl Ebeling
    The practical application of retiming to the design of high-performance systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:288-295 [Conf]
  24. Scott Hauck, Gaetano Borriello, Carl Ebeling
    Mesh Routing Topologies for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:170-177 [Conf]
  25. Carl Ebeling, Andrew J. Palay
    The Design and Implementation of a VLSI Chess Move Generator. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:74-80 [Conf]
  26. Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Lawrence Snyder
    CRANIUM: An Interface for Message Passing on Adaptive Packet Routing Networks. [Citation Graph (0, 0)][DBLP]
    PCRCW, 1994, pp:266-280 [Conf]
  27. Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Lawrence Snyder
    ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing. [Citation Graph (0, 0)][DBLP]
    PCRCW, 1997, pp:247-260 [Conf]
  28. Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille
    The chaos router chip: design and implementation of an adaptive router. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:311-320 [Conf]
  29. Hans J. Berliner, Carl Ebeling
    The SUPREM Architecture: A New Intelligent Paradigm. [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 1986, v:28, n:1, pp:3-8 [Journal]
  30. Hans J. Berliner, Carl Ebeling
    Pattern Knowledge and Search: The SUPREM Architecture. [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 1989, v:38, n:2, pp:161-198 [Journal]
  31. Hans J. Berliner, Gordon Goetsch, Murray Campbell, Carl Ebeling
    Measuring the Performance Potential of Chess Programs. [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 1990, v:43, n:1, pp:7-20 [Journal]
  32. William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
    Seeking Solutions in Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:38-43 [Journal]
  33. Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling
    An FPGA for Implementing Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:3, pp:60-69 [Journal]
  34. Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu
    Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1436-1448 [Journal]
  35. Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie
    Distributed-memory parallel routing for field-programmable gatearrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:850-862 [Journal]
  36. Brian Lockyear, Carl Ebeling
    Optimal retiming of level-clocked circuits using symmetric clock schedules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1097-1109 [Journal]
  37. Akshay Sharma, Carl Ebeling, Scott Hauck
    PipeRoute: a pipelining-aware router for reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:518-532 [Journal]
  38. Tony DeRose, Mary L. Bailey, Bill Barnard, Robert Cypher, David Dobrikin, Carl Ebeling, Smaragda Konstantinidou, Larry McMurchie, Haim Mizrahi, Bill Yost
    Apex: two architectures for generating parametric curves and surfaces. [Citation Graph (0, 0)][DBLP]
    The Visual Computer, 1989, v:5, n:5, pp:264-276 [Journal]
  39. Allan Carroll, Carl Ebeling
    Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  40. Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns
    The Triptych FPGA architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:4, pp:491-501 [Journal]
  41. Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns
    Placement and routing tools for the Triptych FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:4, pp:473-482 [Journal]
  42. Scott Hauck, Gaetano Borriello, Carl Ebeling
    Mesh routing topologies for multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:400-408 [Journal]

  43. SPR: an architecture-adaptive CGRA mapping tool. [Citation Graph (, )][DBLP]


  44. Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays. [Citation Graph (, )][DBLP]


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