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Publications of Author

1. Vijay Sundararajan, Keshab K. Parhi
   Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1999, pp:170-185 [Conf]
   
2. Vijay Sundararajan, Keshab K. Parhi
   Synthesis of low power folded programmable coefficient FIR digital filters (short paper). [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:153-156 [Conf]
   
3. Vijay Sundararajan, Keshab K. Parhi
   Data transmission over a bus with peak-limited transition activity. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:221-224 [Conf]
   
4. Vijay Sundararajan, Keshab K. Parhi
   Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:72-75 [Conf]
   
5. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
   MINFLOTRANSIT: min-cost flow based transistor sizing tool. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:649-664 [Conf]
   
6. Vijay Sundararajan, Keshab K. Parhi
   Reducing bus transition activity by limited weight coding with codeword slimming. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2000, pp:13-16 [Conf]
   
7. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
   Marsh: min-area retiming with setup and hold constraints. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1999, pp:2-6 [Conf]
   
8. Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi
   A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers. [Citation Graph (0, 0)][DBLP]
   ICIP (1), 1997, pp:632-635 [Conf]
   
9. Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
   Energy efficient signaling in DSM CMOS technology. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2001, pp:411-414 [Conf]
   
10. Vijay Sundararajan, Keshab K. Parhi
    Low power synthesis of dual threshold voltage CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:139-144 [Conf]
    
11. Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
    Energy Efficient Signaling in Deep Submicron CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:319-324 [Conf]
    
12. Michael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi
    Vector processing of wavelet coefficients for robust image denoising. [Citation Graph (0, 0)][DBLP]
    Image Vision Comput., 2001, v:19, n:7, pp:435-450 [Journal]
    
13. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
    Fast and exact transistor sizing based on iterative relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:568-581 [Journal]
    
14. Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
    A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:3, pp:273-289 [Journal]
    
15. 
    Optimal power allocation for sum capacity of a slotted three-cell system. [Citation Graph (, )][DBLP]